Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
1999-08-31
2002-05-21
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C713S400000, C713S600000, C365S221000, C375S354000
Reexamination Certificate
active
06393502
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to data communications, and more particularly to a system and method for initiating a serial data transfer between a first device clocked according to a first clock and a second device clocked according to a second clock.
2. Description of the Related Art
In computer systems, especially computer systems including devices that may operate according to differing internal clocks with different clock rates, some mechanism is needed to assure that data transfers can occur between the devices. Typically, synchronous transfers are used to guarantee that data transferred from one device to another is received properly. In a synchronous transfer, the clocking signal is generated by the sending device and transmitted along with the data, so that the data can be properly clocked as sent. When the sending and receiving devices operate according to different clock rates, data transfers are usually limited to the clock rate of the slower device.
One solution to speeding up transfer rates is to use an asynchronous transfer method so that high transfer rates may be achieved between devices operating at different clock rates. In an asynchronous transfer, the clock is not transmitted with the data. One problem that arises is that the asynchronous transfers must be initiated between the devices. What is needed is a system and method for transmitting a data stream between devices operating in differing clock domains, which may have differing clock rates.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a system and method for transferring a data stream between devices having different clock domains. In an exemplary computer system, one or more processors are each coupled to a bridge through separate high speed connections, which in one embodiment each include a pair of unidirectional address buses with respective source-synchronous clock lines and a bi-directional data bus with attendant source-synchronous clock lines. System memory and graphics may also be coupled to the bridge, as well as an input/output bus.
Broadly speaking, a method is contemplated for initiating a serial data stream between a transmitter and a receiver. The transmitter operates according to at least a first clock having a first clock rate, and the receiver operates according to at least a second clock having a second clock rate. A ratio between the second clock rate and the first clock rate is an integer number greater than or equal to one. The method comprises providing a first state over a serial line between the transmitter and the receiver. The method also includes providing one or more start bits over the serial line. The start bits indicate a second state different from the first state. The method also provides one or more ratio bits over the serial line after the start bit. The ratio bits indicate the ratio between the second clock rate and the first clock rate. The method receives the one or more start bits. Using a transition between the first state and the second state evident in receiving each of the start bits, the method receives the one or more ratio bits. The method also includes receiving a remainder of the serial data stream at appropriate intervals of the second clock rate.
A computer system is also contemplated. Broadly speaking, the computer system comprises a memory, logic, and at least one processor. The memory is configured to tore initialization information for the computer system. The initialization information begins with a start bit and a ratio bit. The ratio bit is encoded with the ratio between a second clock rate and a first clock rate. The logic is coupled to the memory for transmitting the initialization information. The logic is configured to operate according to the first clock rate and to transmit the initialization information at the first clock rate. The processor is coupled to receive a first system clock operating at the first clock rate and a second system clock operating at the second clock rate. The processor is configured to operate according to the second system clock. The processor is further coupled to the logic with a serial line over which to receive the initialization information. The logic is configured to transmit the initialization information over the serial line to the processor. The logic is further configured to transmit a first state over the serial line prior to the start bit. The start bit includes a second state different from the first state. The processor is further configured to receive the start bit and to use a transition between the first state and the second state evident in receiving the start bit to receive the ratio bit. The processor is further configured to decode the ratio bit to determine the first clock rate in order to receive the remainder of the initialization information from the logic.
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Madrid Philip Enrique
Meyer Derrick R.
Elamin Abdelmoniem
Gaffin Jeffrey
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