Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-03-04
2008-03-04
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S154000, C711S170000, C712S205000
Reexamination Certificate
active
07340566
ABSTRACT:
Described is a system and method for initializing other memory from block oriented NAND flash by central processing units (CPUs) designed for non-NAND flash. The system employs a sequential loader that avoids the use of branches, loops, and the like, to enable a portion of the sequential loader to be sequentially fetched and executed by the CPU. The fetched and executed portion of the sequential loader is configured to copy additional instructions from NAND flash into random-access memory, such that the CPU may be fully booted from the sequential loader by executing code that has been copied into the random-access memory.
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Geiger Avi R.
Voth David William
Bradley Matthew
Merchant & Gould P.C.
Microsoft Corporation
Peugh Brian R.
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