Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2009-01-05
2010-06-29
Ellis, Kevin L (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S710000
Reexamination Certificate
active
07747915
ABSTRACT:
A system and method for increasing the yield of integrated circuits containing memory partitions the memory into regions and then independently tests each region to determine which, if any, of the memory regions contain one or more memory failures. The test results are stored for later retrieval. Prior to using the memory, software retrieves the test results and uses only the memory sections that contain no memory failures. A consequence of this approach is that integrated circuits containing memory that would have been discarded for containing memory failures now may be used. This approach also does not significantly impact die area.
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Rubenstein Oren
Tamasi Anthony M.
Treichler Sean J.
Vegesna Srihari
Wu Jue
Ellis Kevin L
Gandhi Dipakkumar
NVIDIA Corporation
Patterson & Sheridan LLP
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