Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-09-05
2006-09-05
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C702S181000, C714S726000
Reexamination Certificate
active
07103859
ABSTRACT:
A testability analysis system analyzes testability by evaluating controllability and observability at the level of a hardware functional description independent of architecture. The testability analysis system comprises: an input part inputting functional description data to define a hardware function; a register variable identifying part identifying register variables whereby memory elements such as a flip-flop in said functional description data are inferred; a random pattern generator applying random patterns to the register variable identified by said register variable identifying part; a simulator conducting a simulation on an event caused by applying the random patterns; and an analysis part analyzing a cause of decrease of a fault coverage by LogicBIST, which is mainly caused by the difficulty of detecting faults by the random pattern test that PRPG (Pseudo Random Pattern Generator) of the Scan-Based LogicBIST executes, based upon toggle rates and simulation events of variables (such as net and bus) in said functional description data in accordance with a result of said simulation.
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Boubezari, S. et al., Testability Analysis and Test-Point Insertion in RTL VHDL Specifications for Scan-Based BIST, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, Issue 9, pp. 1377-1340, Sep. 1999.
Claims, Abstract and Drawings of U.S. Appl. No. 10/118,254, filed Apr. 9, 2002.
Cooper & Dunham LLP
Lam Nelson
Ricoh & Company, Ltd.
Thompson A. M.
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