Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2007-05-22
2007-05-22
Verbrugge, Kevin (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S005000, C711S170000, C711S202000
Reexamination Certificate
active
10850803
ABSTRACT:
A memory system having multiple memory devices reduces average access latency by enabling different latencies for different regions of physical memory, providing an address map conducive to placing frequently accessed memory addresses into the lowest latency regions of physical memory; and assigning the frequently accessed memory addresses to the lowest latency regions of physical memory.
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Tsang Brian H.
Woo Steven C.
Morgan & Lewis & Bockius, LLP
Rambus Inc.
Verbrugge Kevin
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