Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-07-16
2002-06-11
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06405350
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to system and a method for improving crosstalk errors such as LSI or PWB (printed wiring board).
DESCRIPTION OF THE RELATED ART
As prior-art publications pertinent to the present invention, reference is made to the following publications:
(1) JP Patent Kokai JP-A-7-135457; and
(2) “CAD of Logic Devices”, edited by Kozo Kinoshita, IPSJ(Information Processing Society of Japan), issued Mar. 20, 1981, pages 31 to 62.
If, in the prior-art placing system, the wiring pitch is of a large magnitude, it has been unnecessary to take account of the cross-talk by the neighboring wiring. However, as the wiring becomes finer in pitch with pattern miniaturization, the effect of the crosstalk becomes non-negligible. Thus, after end of the placing and wiring, the cross-talk by the neighboring wiring is calculated to make cross-talk analysis to effect manual correction of the net itself which has caused the crosstalk errors or the wiring pattern of the neighboring net responsible for crosstalk.
Alternatively, the wiring connection designing is manually preliminarily adjusted to preclude an elongated net liable to cause crosstalk errors or superfluous repeater buffers are inserted during logical designing to preclude the occurrence of an unnecessarily long net liable to the effect of crosstalk.
In the wiring designing, automatic wiring means have also been used to suppress occurrence of crosstalk errors for controlling line length for preventing the wiring route of each net from exceeding a pre-set linear length.
SUMMARY OF THE DISCLOSURE
However, the above-described techniques suffer from the following drawbacks:
The first drawback is that, after detecting the crosstalk error, the resulting wiring of the net or the neighboring net need to be corrected manually.
The reason is that not only is a large number of manual wiring correction steps required, but also the net to be corrected has a long wiring length itself , so that, depending on the degree of wiring congestion, the wiring correction by itself is insufficient to remove and improve the crosstalk error.
The second drawback is that a manual placing and wiring designing needs to be adjusted preliminarily to eliminate crosstalk errors.
The reason is that a large number of laborious steps are required for the manual placing and wiring operation and the layout (floor plan) needs to be taken into account since the time of logical designing, thus placing limitations on designing to increase designing difficulties to result in a newly increased number of steps.
The third drawback is that excess repeater buffers are inserted during logical designing.
The reason is that the numerous steps required for logical correction and excess repeater buffers worsen the routability or increase the power consumption.
As a fourth drawback there is a problem caused in case where the occurrence of the crosstalk error is suppressed using automatic wiring means which effectuates line length control to prevent the wiring route of each net in the wiring designing from exceeding a pre-set linear wiring length.
That is, since the wiring length of the net itself is long so that, depending on the degree of wiring congestion, there are occasions wherein the limitation on the wiring length alone is insufficient to eliminate or improve the crosstalk error, or the bending or detour of the wiring occurs to the extent more than is necessary to worsen the routability.
It is therefore an object of the present invention to provide a more accurate system and method for improving the crosstalk error whereby the amount of the crosstalk can be calculated only for the net under inspection liable to affect neighboring nets by taking into account the switching timing in detecting the crosstalk errors.
It is another object of the present invention to provide a system and method in which a delay gate is inserted partway on the wiring route of a neighboring affected net or a net on the path to which belongs the neighboring net, among the nets found to be undergoing crosstalk error by the results of layout of usual placing and wiring, to shift the timing to reduce the number of manual correction steps of the crosstalk error for improving the crosstalk error.
A further object of the present invention is as follows: That is, if the crosstalk error is to be improved only by the correction of the wiring route of the net, there are occasions wherein the error cannot be eliminated or improved depending on the degree of the wiring congestion if the wiring length of the net to be corrected is long, whereas, with the method of delaying the timing of the neighboring net by the delay gate, the wiring congested portion can be evaded thus increasing the possibility of improvement in the crosstalk error.
It is also necessary to prevent the routability from being lowered or to prevent the power consumption from being increased as a result of the insertion of excess repeater buffers during logical designing.
It is also necessary to overcome the limitations on the removal and improvement of the crosstalk error in the wiring congestion area and to suppress routability otherwise caused by bending of the wiring to an extent more than is necessary or detour in case of using automatic wiring means controlling the line length to prevent the net wiring route from being placed in excess of a pre-set line length.
There is provided a system for automatically improving and removing the crosstalk error for reducing the number of designing steps.
The switching timing of each net is detected from the results of path delay analysis and crosstalk analysis is carried out so as to take account of the overlap of the switching timing between a net under inspection and a neighboring net. A delay gate insertion unit inserts a delay gate to a neighboring net having timing overlap with the net under inspection undergoing crosstalk error as detected or a net on a path to which belongs the neighboring net. The delay gate inserted is such a delay gate as can improve the crosstalk and as does not cause path delay error. The delay gate inserted by the delay gate placing unit is placed on the route of the net at such a position as can improve the crosstalk error of the net under inspection. An incremental wiring unit re-wires a net divided by the insertion and placing of the delay gate and a net affected by the insertion and placing of the delay gate to improve the crosstalk error automatically.
In an aspect of the present invention, there is provided a crosstalk error improving system comprising:
(a) means for detecting switching timing of each net from the results of path delay analysis to execute crosstalk analysis which takes into account overlap of the switching timing of the net under detection with a neighboring net;
(b) means for inserting a delay gate into a neighboring net having timing overlap with the net under detection undergoing crosstalk error with the net under detection or with a net on a path to which belongs the neighboring net, said delay gate being capable of improving the crosstalk error without causing a path delay error;
(c) means for placing the inserted delay gate at a position on the route of the net capable of improving the crosstalk error of the net under detection; and
(d) means for re-wiring the net divided by the insertion and placing of the delay gate and an affected net.
In a second aspect of the present invention, there is provided a crosstalk error improving system comprising, in a layout designing for LSI or PWB. The system comprises:
(a) logical/library inputting means for inputting:
logical connection information between blocks making up a circuit,
physical information of block placing results and/or inter-block connection wiring results,
delay library information comprising parameters for calculating block internal delay and/or wiring delay required for delay analysis, and
library information for crosstalk analysis comprising parameters for calculating crosstalk magnitude required for crosstalk analysis;
(b) path delay limit value inputting means for in
NEC Corporation
Siek Vuthe
Sughrue & Mion, PLLC
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