System and method for improving channel hardware performance for

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition

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Details

711154, 39518204, 395824, G11B 1722, G06F 1312

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active

058931384

ABSTRACT:
Disclosed is an array controller for controlling the transfer of data from a host system to an array of data storage devices, comprising a processor connected via a local bus to a data buffer in which data is staged during said transfer. The array controller is provided with a buffer controller for controlling the operation of the buffer and is further provided with channel hardware for manifesting a plurality of data channels, selectable by the local bus address, over which data is transferred in and out of the data buffer.

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