Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2011-01-11
2011-01-11
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S016000
Reexamination Certificate
active
07870515
ABSTRACT:
A method for hierarchical analysis of electronic circuits comprises selecting a first one of a plurality of abstraction levels of a general design model (GDM). The GDM comprises a first design description of electronic circuits at a plurality of abstraction levels and a plurality of foci, organized into sub-blocks. The method selects a first focus of the plurality of foci to select a first sub-block. The method identifies incomplete electronic circuits in the selected first sub-block. The method generates a second design description of the first sub-block to exclude identified incomplete electronic circuits, wherein the second design description is suitable for electronic design analysis (EDA). The method stores the generated second design description for subsequent use. Subsequent iterations thereby include all components of circuits that were incomplete in prior iterations.
REFERENCES:
patent: 5703798 (1997-12-01), Dhar
patent: 5923569 (1999-07-01), Kumashiro et al.
patent: 6044214 (2000-03-01), Kimura et al.
patent: 6301692 (2001-10-01), Kumashiro et al.
patent: 6408265 (2002-06-01), Schultz et al.
patent: 6564355 (2003-05-01), Smith et al.
patent: 7013440 (2006-03-01), Croix
patent: 7117461 (2006-10-01), Srinivasan
patent: 05028219 (1993-02-01), None
patent: 09114875 (1997-05-01), None
patent: 2000353184 (2000-12-01), None
Shinichi et al., automated English translation of Japanese Patent Application Publication No. 09-114875, published Feb. 5, 1997, automatically translated on May 9, 2010 at Japan Patent Office website http://www.ipdl.inpit.go.jp/homepg—e.ipdl.
Andreas Kuehlmann et al., “Verity—a Formal Verification Program for Custom CMOS Circuits”, IBM Journal on Research and Development, Jan. 1995, IBM Thomas J. Watson Research Center, Yorktown Heights, N. Y., pp. 1-28.
Ledalla Ravichander
Rao Vasant
Shephard, III Philip G.
Soreff Jeffrey P.
Caldwell, Esq. Patrick E.
International Business Machines - Corporation
Kik Phallaka
The Caldwell Firm, LLC
LandOfFree
System and method for improved hierarchical analysis of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for improved hierarchical analysis of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for improved hierarchical analysis of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2651672