System and method for implementing row redundancy with...

Details System and method for implementing row redundancy with... System and method for implementing row redundancy with...

2007-11-19

2009-10-27

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230030, C365S230060, C365S230010

Reexamination Certificate

active

07609569

ABSTRACT:
A system for implementing row redundancy in integrated circuit memory devices includes one or more main subarrays having word line, bit line and memory cell devices, each of the one or more main subarrays including a set of support circuitry associated therewith. A discrete, redundant subarray is associated with the main subarrays, and also includes a set of support circuitry associated therewith. A common global bit line is shared by the main subarrays and the redundant subarray, and redundancy steering control circuitry is associated with the main subarrays and the redundant subarray. The redundancy steering control circuitry is configured such that word line activation of the main subarrays and the redundant subarray is performed in parallel with address compare operations performed by the redundancy steering control circuitry.

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