Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-06-08
2004-08-17
Torres, Joseph D. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
06779141
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to testing a static random access memory (SRAM) unit. More particularly, the present invention relates to memory testing of an SRAM unit having a write control module with write enable control and a read control module with no read enable control.
2. The Background Art
Memory test algorithms are used to provide highly; efficient testing for static random access memory (SRAM) units. An illustrative example of a variety of memory test algorithms include the 2N, 6N or 12N march test algorithms which are used to test SRAM components. These march test algorithms include testing internal RAM data integrity at the CPU manufacturing and debug stage and for field testing and diagnostic testing.
By way of example and not of limitation, the 6N march test algorithm uses a specific data background and the complement of the specific data background in a read/write manner. The 6N march test consists of six(6) read/write cycles which are accomplished in three passes. Those with ordinary skill in the art shall appreciate that the six read/write operations are identified as:
↑W
o
, ↑(R
o
W
1
), ↓(R
1
W
o
R
o
)
The first march element (↑W
o
) writes a particular data background of ones and zeros into the SRAM. The first march element writes addresses from lower to higher memory addresses. The write operation of the first march element is identified as W
o
. The upward arrow, ↑, is used to designate performing either read or write operations from lower to higher memory addresses.
The second march element, ↑(R
o
W
1
), performs its read and write operations by reading and writing from the lower memory addresses to the higher memory addresses. During the first operation of the second march element, the data background from the first march test is read. This first operation of the second march element is identified as R
o
. During the second operation of the second march element, the complement of the data background is written to the SRAM addresses. The second operation of the second march element is identified as W
1
. The complement of the data background is tested to verify that the SRAM cells containing a “one” can store a “zero” and vice versa.
The third march element, ↑(R
1
W
o
R
o
), performs its read and write operation by reading and writing from the higher memory addresses to the lower memory addresses. The downward arrow, ↓, is used to represent performing read and write operations from higher to lower memory addresses. During the first operation of the third march element, the data background from the write complement, W
1
, completed in the previous march element is read. This first operation of the third march element is identified as R
1
. During the second operation of the third march element, the original data background is written back to the same memory locations. This second operation of the third march element is identified as W
0
. During the third operation of the third march element, the original data background is read from the same memory locations to verify the contents of each location. This third operation is identified as R
0
.
Referring to
FIG. 1
, there is shown a block diagram of a prior art testing system
10
having one input data register
12
which is scannable and used for storing data to be written into SRAM
14
. The prior art teaches the use of a single input register
12
in conjunction with the memory test algorithm for conducting SRAM diagnostic testing. The initial data background from the single input register is written into each data line of the SRAM
14
. The input data register
12
may be comprised of a plurality of flip-flops and/or macros. A macro comprises a plurality of flip-flops. After the initial data background is written into the data line, the ↑W
o
operation is completed. The complement of the ↑W
o
operation, i.e. ↑W
1
, is generated by inverting the initial data background (not shown) and scanning in the inverted data background to the single input register. Additionally, it is well known that two input data registers may also be used to write into the datalines of a SRAM.
Complex integrated circuits are tested by generating a comparison between known output patterns and a device under test pattern. The output pattern is generated with input stimuli, and those same input stimuli are presented on the device under test. Comparisons are made cycle by cycle with an option to ignore certain pins, time or patterns. If the device response and the output response are not in agreement, the device is usually considered defective.
Those of ordinary skill in the art shall appreciate that memory testing with a memory test algorithm typically uses a built-in self-test (BIST) logic. BIST logic is built into a circuit to perform testing without the use of an external tester for pattern generation and comparison purposes. The BIST logic provides the ability to categorize failures and separate good from bad units. Additionally, BIST logic supplies clocks to the device and determines the pass/fail from the outputs of the device.
The BIST capability can be implemented on virtually any size CPU block. With BIST a single bit defect can easily be detected using self-testing techniques. Single-point defects in the CPU block from the manufacturing process can show up as a single transistor failure in a RAM or they may be somewhat more complex. If a single-point defect happens to be in the decoder section or in a row or column within the RAM, the device may be nonfunctional.
SUMMARY OF THE INVENTION
The present invention provides a system and method for performing a march test algorithm on an SRAM unit having a write control module with write ports and write enable control, and a read control module with read ports and no read enable control. The system of the present invention includes an address offset unit which communicates with the SRAM unit to avoid reading and writing simultaneously to the same addresses. The SRAM unit includes a plurality of SRAM storage cells, a write control module, a read control module, a write address control, a read address control, and an address decoder.
The address offset unit includes a memory test controller and an address offset module. The memory test controller is configured to communicate a memory test algorithm to the SRAM unit. The address offset module resides within the memory test controller and is configured to send separate signals to the read control module and the write control module to avoid simultaneously reading and writing to the same address. Preferably, the signals generated by the address offset system are communicated to the SRAM unit as part of a programmed march test algorithm which is resident on the CPU as built-in-self-test (BIST) logic.
The present invention also provides an address offset method which performs an illustrative march test algorithm for an SRAM unit having no read enable control. The illustrative march test algorithm is a 6N march test algorithm having a first march, a second march and a third march. The method includes conducting a first march element and a second march element by reading and writing from lower address to higher addresses by incrementing. During the first march element and the second march element, the read operation is offset from the write operation by being one step ahead of the write operation. During the third march element reading and writing is accomplished by reading and writing from the higher addresses to the lower addresses by decrementing. Alternatively, other march test algorithms may be employed.
REFERENCES:
patent: 5311476 (1994-05-01), Kajimoto et al.
patent: 5384784 (1995-01-01), Mori et al.
patent: 5469443 (1995-11-01), Saxena
patent: 5506959 (1996-04-01), Cockburn
patent: 5513318 (1996-04-01), van de Goor et al.
patent: 5537632 (1996-07-01), Gorshe
patent: 5604756 (1997-02-01), Kawata
patent: 5734613 (1998-03-01), Gibson
patent: 6046946 (2000-04-01), Nadeau-Dostie et al.
patent: 6070256 (2000-05-01), W
Martine & Penilla LLP
Sun Microsystems Inc.
Torres Joseph D.
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