Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-10-04
2002-07-16
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S748000, C714S751000, C714S758000, C714S776000
Reexamination Certificate
active
06421803
ABSTRACT:
BACKGROUND OF THE PRESENT INVENTION
1. Field of the Invention
The present invention relates generally to telecommunications systems and methods for reliable transmission of information, and specifically to error control coding to ensure the reliability of transmitted information.
2. Background and Objects of the Present Invention
There are many applications where large volumes of digital data must be transmitted and received in a substantially error free manner. In cellular telecommunications and satellite communications systems, in particular, it is imperative that the transmission of digital data over the air interface be completed in as accurate a manner as is possible. Accurate transmission and reception of digital data has, however, been difficult because the communications channels utilized for data transmissions over the air interface are plagued by error introducing factors. For example, such errors may be attributable to transient conditions in the channel, such as noise and distortion, or they may be due to recurrent conditions attributable to defects in the channel. The existence of transient conditions or defects results in instances where the digital data is not transmitted properly or cannot be reliably received.
Digital data is often transmitted in packets (or blocks or frames), in which each packet includes a number of information bytes followed by a frame check sequence of parity check bits (PCBs). The errors that typically occur in the transmission and reception of digital data are of two types: “random” channel errors and “burst” channel errors. Random channel errors are errors that occur independent of one another and are uniformly spread in a packet, while burst channel errors are errors that occur in clusters. The PCBs in each data packet are used to detect when and where a channel error has been introduced into the data packet.
Considerable attention has been directed towards discovering methods for addressing the problems concerning errors which typically accompany data transmission activities over the air interface. For example, two common techniques of error correction include Forward Error Correction (FEC) and Automatic Repeat Request (ARQ). The FEC error correction technique adds redundant information in the transmitter, which is used by the receiver to correct transmission errors, whereas in the (ARQ) error correction technique, the data is encoded in such a way that errors in the data packet can be detected, but not corrected. With ARQ, when errors are detected, the receiver requests retransmission of those erroneously received data packets.
One common way of detecting errors is to include error detecting PCBs, such as a Cyclic Redundancy Check (CRC) code, with the data packet. The CRC code is generated from the information included in the data packet. At the receiver, the receiver uses the information included in the received data packet to generate an additional CRC code. If the CRC code generated by the receiver matches the CRC code included with the received data packet, the data packet is accepted as correctly received. If not, the receiver requests retransmission of that data packet. It should be understood that the error could be with the data packet or with the CRC code itself. However, since the CRC code and data packet are considered one unit, an error to either is considered an error to the whole unit.
If the bit error rate (BER) on the communications channel is relatively small, the ARQ technique will give a high throughput for feasible packet lengths. However, if the BER is increased, the throughout will be heavily reduced due to the increased number of retransmissions needed. Therefore, typically, a combination of FEC and ARQ techniques are applied in order to have a reliable link without sacrificing too much in average through-put. This combination of ARQ and FEC is referred to as Hybrid ARQ.
For example, in order to improve the performance for the ARQ technique when the BER is high, Hybrid ARQ type-I techniques can be used. In a Hybrid ARQ type-I technique, the data is encoded such that in addition to error detection, correction of the most likely errors can be performed at the receiver. Only the most likely errors, e.g., error patterns with only a few bits in error, are corrected at the receiver, which reduces the number of retransmissions. The rare error patterns are detected, and retransmission of those data packets with rare errors is requested. Therefore, the effective data rate of the packet can be kept relatively high. Hybrid ARQ type-I techniques are best suited for channels where the BER is relatively constant.
However, there are many practical cases where the BER is not constant, but rather varies considerably. The reasons for this variance in BER can include, for instance, an interferer present during a part of the packet, but not during another part of the packet. The effect of this variance can be either a good channel, such that no error correction is needed, or an extremely bad channel, such that a very powerful code (implying low rate) would be needed. Hybrid ARQ type-I techniques do not perform well when the channel is good, because the error correcting capability is not needed. In addition, when the channel is extremely bad, which implies that excessive rare error patterns might be present, the error correcting capability of the Hybrid ARQ type-I technique might not be sufficient.
In these cases of BER variance, a Hybrid ARQ type-II technique can be employed. The Hybrid ARQ type-II technique adapts the ARQ technique to the actual channel conditions. First, a data packet is sent with a block of PCBs for error detection only. If no errors are detected by the receiver, the packet is considered correctly received. If, however, errors are detected, the received packet is buffered, and the receiver requests the transmitter to transmit another block of PCBs, which can be used, together with the previously received block of PCBS, to perform error correction. Thus, error correction is only performed when it is actually needed. However, as with the conventional ARQ technique, the ARQ type-II technique introduces additional delay due to the retransmission of the PCBs.
It is, therefore, an object of the present invention to provide for both error detection and error correction of data packets without the need for retransmission of the data packet or parity check bits associated with the data packet.
It is a further object of the present invention to provide error correction only for those data packets received incorrectly.
SUMMARY OF THE INVENTION
The present invention is directed to telecommunications systems and methods for performing error detection on data packets at a receiver, and for performing error correction on only those data packets that were received in error, without the need for retransmission of the data packets or parity checking bits. The complete data packet to be transmitted is first divided into a number of blocks denoted data units (DUs). The DUs are encoded for both error detection and error correction. Subsequently, the error correction parity check bits for the DUs of the complete data packet are combined into one or more blocks, and likewise, the error detection parity check bits are preferably combined into one or more separate blocks. Thereafter, a transmitter transmits the DUs and the block(s) containing the combined parity check bits to the receiver. When the receiver decodes the DUs, the receiver checks for errors in each of the DUs. For each DU that does not contain any errors, the parity check bits for error correction for that DU are generated and their effect on the combined parity check bits for error correction removed. Thereafter, the parity check bits for error correction, which now only contains information about the DUs actually in error, are used in an attempt to correct the erroneous DUs. Thus, the parity check bits for error correction are only used for those DUs determined to have errors, and no error correcting capability is wasted on those DUs that have been correctly received.
Persson Joakim
Wilhelmsson Leif
Jenkens & Gilchrist P.C.
Moise Emmanuel L.
Telefonaktiebolaget L M Ericsson (publ)
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