Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2008-04-29
2008-04-29
Chase, Shelly A (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
07366969
ABSTRACT:
Various methods and systems for implementing Reed Solomon multiplication sections from exclusive-OR (XOR) logic are disclosed. For example, a system includes a Reed Solomon multiplication section, which includes XOR-based logic. The XOR-based logic includes an input, an output, and one or more XOR gates. A symbol X is received at the input of the XOR-based logic. The one or more XOR gates are coupled to generate a product of a power of α and X at the output, wherein α is a root of a primitive polynomial of a Reed Solomon code. Such a Reed Solomon multiplication section, which can include one or more multipliers implemented using XOR-based logic, can be included in a Reed Solomon encoder or decoder.
REFERENCES:
patent: 5946328 (1999-08-01), Cox et al.
patent: 6990624 (2006-01-01), Dohmen et al.
Gao et al., Custom VLSI design of efficient low latency and low power finite field multiplier for Reed Solomon Codec, 2001, IEEE, p. 574-577.
Hsu et al., A comparison ov VLSI architecture of finite filed multipliers using dual, normal, or standard bases, Jun. 1998, IEEE Trans. on Computers, vol. 37, No. 6, p. 735-739.
Dong Qiujie
Thurston Andrew J.
Brock Brenna A.
Campbell Stephenson LLP
Chase Shelly A
Cisco Technology Inc.
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