Electrical computers and digital data processing systems: input/ – Interrupt processing – Multimode interrupt processing
Reexamination Certificate
2000-11-17
2004-01-20
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Interrupt processing
Multimode interrupt processing
C710S260000, C710S264000, C340S870030
Reexamination Certificate
active
06681281
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of computer systems and, more particularly, to bus interrupt systems in computer systems.
2. Description of the Related Art
Computer systems may include many devices that perform different functions. Each device may perform general functions or specific functions depending on the device the type of system. The devices typically interact with the central processing unit (CPU) in the system. To do so, many of the devices may be coupled to a bus that may be coupled to the CPU. These devices may be referred to as bus devices. A bus may be directly coupled to the CPU or may be coupled to the CPU using a bus bridge. Examples of busses may include a PCI bus, an EISA/ISA bus, and a USB bus. Each of these busses may conform to a bus protocol that may be described in a bus specification. A bus devices may include hardware or software to allow it to conform to a bus protocol.
In certain bus architectures, a bus device may signal its need to communicate with a CPU by using an interrupt. A bus device may convey an interrupt signal to a bus controller using a dedicated interrupt line for that bus device. The bus device may convey an interrupt signal by simply asserting its interrupt line. A bus controller may receive interrupt signals from bus devices and, in the case of conflicting interrupt requests, may arbitrate between the interrupt requests and grant an interrupt to one of the bus devices that corresponds to one of the conflicting interrupt requests. The manner in which a bus controller arbitrates between conflicting interrupt requests may vary between computer systems according to an arbitration scheme used by the bus controller. The arbitration scheme may be a round robin system or a system where certain bus devices are given priority over other types of bus devices, for example. The bus device whose interrupt request is granted may communicate with the CPU.
Recent bus devices, such as software modems, may perform operations that are increasingly time critical and may require faster responses to interrupt requests. Arbitration schemes used by bus controllers, however, may not be sensitive to these increasing needs. When interrupt requests conflict, problems may occur where a bus controller grants an interrupt to a bus device whose needs may be less time sensitive than another bus device. In the case of a software modem, for example, a connection may be dropped if an interrupt request of the modem is not granted over a conflicting interrupt request of another device. This type of situation may be avoidable if a bus controller was able to determine that one bus device has a more time sensitive interrupt request than another when interrupt requests conflict. A system and method is needed to allow a bus device to indicate an interrupt priority level to a bus controller. Further, a system and method for allowing a bus device to indicate an interrupt priority level to a bus controller is needed that may be incorporated into existing bus architectures.
SUMMARY
The problems outlined above are in large part solved by the use of the system and method described herein. Generally speaking, a system and method for implementing a multi-level interrupt scheme in a computer system is provided. Bus devices and a bus controller may be coupled to a shared bus in a computer system. The bus may include an interrupt line for each bus device coupled to the bus. A bus device may be configured to convey an interrupt using its designated interrupt line. Each bus device may be configured to convey different types of interrupt signals on its interrupt line depending on an interrupt priority level of a given interrupt. The bus controller may be configured to receive interrupt signals from each bus device coupled to the bus and may arbitrate amongst the interrupt signals based on the interrupt priority level of each interrupt signal. The bus controller may grant the interrupt that corresponds to the highest priority level. If multiple interrupts correspond to the same highest priority level in a group of interrupts, then the bus controller may use any suitable arbitration scheme to grant an interrupt.
The system and method described herein may provide performance advantages over other systems and methods. The use of a multi-level interrupt scheme may allow a bus controller to more appropriately grant an interrupt among a group of conflicting interrupt requests by determining the priority of each interrupt request. By determining the priority of each of a group of interrupt requests, a bus controller may ensure that a bus device receives timely servicing of its interrupt. The system and method described herein may also be implemented using existing bus hardware. A bus device may indicate different interrupt priority levels by conveying different signals to a bus controller on an existing interrupt line. Accordingly, the system and method described herein may be incorporated into existing bus systems.
In one embodiment, a bus device may convey interrupt signals with different frequencies to indicate an interrupt priority level. The bus device may convey an interrupt signal with a first frequency to indicate a first priority level and may convey the interrupt signal with a second frequency to indicate a second priority level. The use of other signal frequencies may indicate other priority levels. In another embodiment, a bus device may convey interrupt signals with different duty cycles to indicate an interrupt priority level. The bus device may convey an interrupt signal with a first duty cycle to indicate a first priority level and may convey the interrupt signal with a second duty cycle to indicate a second priority level. The use of other pulse duty cycles may indicate other priority levels.
REFERENCES:
patent: 4788639 (1988-11-01), Tamaru
patent: 5125093 (1992-06-01), McFarland
patent: 5392033 (1995-02-01), Oman et al.
patent: 5555420 (1996-09-01), Sarangdhar et al.
patent: 5555430 (1996-09-01), Gephardt et al.
patent: 5758105 (1998-05-01), Kelley et al.
patent: 5828891 (1998-10-01), Benayoun et al.
patent: 5905898 (1999-05-01), Qureshi et al.
patent: 5918057 (1999-06-01), Chou et al.
patent: 6041105 (2000-03-01), Wu et al.
patent: 6070221 (2000-05-01), Nakamura
patent: 6484281 (2002-11-01), Wang et al.
patent: 09244991 (1997-09-01), None
patent: 11232210 (1999-08-01), None
International Search Report application No. PCT/US01/24690, mailed Apr. 24, 2002.
Advanced Micro Devices , Inc.
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Ray Gopal C.
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