Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2006-06-20
2006-06-20
Ellis, Kevin L. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C377S026000
Reexamination Certificate
active
07065607
ABSTRACT:
A counter is provided which can be implemented in flash memory allowing longer life through fewer erasures. The counter is incremented using a method that minimizes bit transitions from 1 to 0. In one embodiment, the counter is implemented in m+n bits. The bits of the counter are grouped into a binary portion of the counter of m bits and a unary portion of the counter of n bits. In order to increment the counter, the unary portion of the counter is incremented first. When the unary portion of the counter reaches a specific value, the binary portion of the counter is incremented. This limits 1 to 0 bit transitions and allows a large range of unique values to be read from the counter. In another embodiment, two unary counters are formed, which dynamically change in size as the counter is incremented.
REFERENCES:
patent: 4947410 (1990-08-01), Lippmann et al.
patent: 5381452 (1995-01-01), Kowalski
patent: 5892900 (1999-04-01), Ginter et al.
patent: 6084935 (2000-07-01), Mather
patent: 6249562 (2001-06-01), Wells
patent: 6687325 (2004-02-01), Wells
England Paul
Peinado Marcus
Ellis Kevin L.
Microsoft Corporation
Woodcock & Washburn LLP
LandOfFree
System and method for implementing a counter does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for implementing a counter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for implementing a counter will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3626660