System and method for implementing a counter

Details System and method for implementing a counter System and method for implementing a counter

2006-06-20

2006-06-20

Ellis, Kevin L. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C377S026000

Reexamination Certificate

active

07065607

ABSTRACT:
A counter is provided which can be implemented in flash memory allowing longer life through fewer erasures. The counter is incremented using a method that minimizes bit transitions from 1 to 0. In one embodiment, the counter is implemented in m+n bits. The bits of the counter are grouped into a binary portion of the counter of m bits and a unary portion of the counter of n bits. In order to increment the counter, the unary portion of the counter is incremented first. When the unary portion of the counter reaches a specific value, the binary portion of the counter is incremented. This limits 1 to 0 bit transitions and allows a large range of unique values to be read from the counter. In another embodiment, two unary counters are formed, which dynamically change in size as the counter is incremented.

REFERENCES:
patent: 4947410 (1990-08-01), Lippmann et al.
patent: 5381452 (1995-01-01), Kowalski
patent: 5892900 (1999-04-01), Ginter et al.
patent: 6084935 (2000-07-01), Mather
patent: 6249562 (2001-06-01), Wells
patent: 6687325 (2004-02-01), Wells

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