Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
2006-04-12
2010-11-23
Tseng, Cheng-Yuan (Department: 2184)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C710S035000, C341S085000
Reexamination Certificate
active
07840726
ABSTRACT:
A system and method is disclosed for programming a field programmable gate array. The system involves the recognition of the next following bit sequence to be transmitted to the FPGA through a general purpose input output device. Once the bit sequence is identified, the data line is only changed at the GPIO in those instances in which the next succeeding data bit in the bit sequences is different from the preceding data bit. In those situations in which the next following bit sequence is not different, the clock line is triggered without the necessity of testing, and changing the logic level of the data line.
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Brelsford Brian L.
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McGary Jon M.
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Tseng Cheng-Yuan
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