Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2007-06-04
2010-11-30
Patel, Nitin C (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S501000
Reexamination Certificate
active
07844849
ABSTRACT:
A system and method for identifying and manipulating logic analyzer data from multiple clock domains is presented. A logic analyzer receives debug data and determines whether the debug data is a full frequency data type, a half frequency data type, or a crossed data type. Once determined, the logic analyzer reconstructs the debug data such that debug condition-matching logic may process the reconstructed data in a full frequency domain. For half frequency data types, the logic analyzer adds masked data values to the data in order to reconstruct the data into to the full frequency domain before processing the data. For crossed data types, the logic analyzer reconstructs the data into its original format before processing the data in a full frequency domain.
REFERENCES:
patent: 2005/0273671 (2005-12-01), Adkisson et al.
Genden Michael Joseph
Spannaus John Fred
International Business Machines - Corporation
Patel Nitin C
Talpis Matthew B.
VanLeeuwen & VanLeeuwen
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