Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1996-05-07
1999-05-18
Chin, Stephen
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
327156, 327261, H03D3/24
Patent
active
059057696
ABSTRACT:
A method and apparatus is disclosed that receives a multi-channel digital serial encoded signal and converting it signal into a synchronized set of binary characters. A charge pump phase-locked loop receives a transmitted reference clock and derives a multi-phase clock from the reference clock. The multi-phase clock is used to control a plurality of multi-bit block assembly circuits. Each assembly circuit receives one channel of the digital signal and produces a multi-bit block or character. The multi-bit block assembly circuit includes an oversampler, a digital phase-locked loop and a byte synchronizer. The oversampler oversamples the received digital signal under control of the multiphase clock and produces a sequence of oversampled binary data. The digital phase-locked loop receives the oversampled data and selects samples from it depending on the skew characteristics of the sample. The byte synchronizer assembles a sequence of selected bits into a bit block, or character. An interchannel synchronizer receives as input the characters produced by each of the multi-bit block assembly circuits, and selectively delays output of the received characters in order to synchronize the characters of each channel with one another.
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A CMOS Serial Link for Fully Duplexed Data Communication, Kyeongho Lee, Sungjoon Kim, Gijung Ahn, and Deog-Kyoon Jeong, 2334c IEICE Transactions on Electronics E78-C(1995) Jun., No. 6, Tokyo, JP; pp. 601-612.
An 800 Mbps Multi-Channel CMOS Serial Link with 3x Oversampling, (May 1, 1995), pp. 451-454.
Jeong Deog-Kyon
Lee Kyeongho
Chin Stephen
Roundtree Joseph
Silicon Image Inc.
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