Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-12-21
2004-02-24
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C710S052000
Reexamination Certificate
active
06697968
ABSTRACT:
A portion of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
RELATED APPLICATIONS
Filed on even date herewith are application Ser. Nos. 09/745,813 and 09/747,046, which have substantially similar or identical disclosure to the disclosure contained herein but which claim different inventions.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to computer system design tools and more particularly to systems and methods for enabling rapid retrieval, use, and analysis of the operations of microprocessors or other instruction processors by providing a record for analyzing the signals present on their busses. Designs are described for on-the-fly removal of useless trace data and for handling multiple trace streams simultaneously to produce a coherent data file.
2. Background Information
In designing computer systems, one needs to have sufficient data about the performance characteristics of the elements of the computer system being used. Instruction processors, particularly, have unique ways of behaving in the presence of varied tasks given them. Accordingly, a system for maintaining a complete record or trace is required to enable the recovery of all data on the instruction processor busses while they handle various tasks in various computer architectures. The variability of the computer architecture can cause sharp differences in the tasks required of the instruction processors. Accordingly, the performance of the instruction processor in the environments of the various possible architecture designs is a critical component of the knowledge required to produce effective computer architecture designs. Such knowledge permits appropriate restructuring of designs by for example, using a larger cache or main memory if system throughput should be improved by such a change under a given set of use assumptions.
One important use of trace data is to use it to simulate a running process on an emulated computer system under design. For the simulation to be valid, steady state run information should be reflected in the trace data from a test system recovered (by using this invention, for example) that can be used in a simulated system for testing the simulated system. As is explained more fully within, obtaining appropriate sample data for running such simulated systems is not feasible with prior art test equipment.
Systems previously or currently used for testing computer system components share common elements with trace systems used to store the output of instruction processors. For example, in a patent issued in 1985 to Babcock, U.S. Pat. No. 4,550,287 (incorporated herein by this reference), a hand held instrument would show the states of wires, thus giving a visual indication of data activity on a tested line. More complex information could be gained by comparing test bit patterns when a microprocessor fault occurred with bit patterns from the microprocessor under test, as was shown in Pri-Tal's U.S. Pat. No. 4,622,699, also incorporated by this reference hereinto. In Song's U.S. Pat. No. 5,850,512, (also incorporated herein by this reference) it was shown that test data can be provided by a testing system and traces of the output can be stored in a bus tester and analyzed. La Joie et al, in U.S. Pat. No. 5,630,048, also incorporated by this reference thereto showed similar functionality to Song, and provided for second monitoring to perform boundary scan testing.
Currently both Agilent Technologies and Tektronix manufacture logic analyzers that can record signals from a processor bus, but neither of these is capable of providing a sufficient length of time for the trace data to reach steady state, a requirement for doing reliable system design analysis. One has to know with some degree of certainty that the cache state is what would normally be expected, and that cannot be achieved within the sub-second of trace data such systems can currently manage. The high end Agilent logic analyzer (model numbers 16555/56/57 or 16700) with either their E2487C or E2496 (for 64 bit words) probes can only achieve at maximum configuration for three probes 32 Mega-entries of storage. While various techniques described herein can make the use of smaller memories more useful, in order to be confident of attaining steady state with a large cache of a several megabytes or so size, it is estimated that 8 gigabytes of trace data would be required. Accordingly the costs of producing test equipment designed like the currently commercially available systems which require a large high speed memory to keep up with the processor bus are commercially untenable.
To reiterate, the problem with using currently available commercial test equipment for large scale test tracing to facilitate computer system design is that none of this equipment is built to accommodate large volumes of data at the natural rate and form in which it is generated. Test blocks of data such as would be available from such test devices, as described or listed above, do not provide sufficiently useful information for facilitating design of the features or arrangements of components of computer architectures. Thus, cache sizes, inter-processor and processor-to-memory pathways, and overall system design can be enhanced by permitting the designer to focus on the important characteristic of how much data is being processed through any given computer and cache architecture design. This contrasts with prior data sets from tracing which provide insight on how the data is being processed or whether it is being processed correctly using a limited signal-by-signal view of a short period of bus usage.
Accordingly there is a strong need to have a cost effective tool for designing high throughput systems, and especially for designing multiprocessor computer systems, that will accurately provide large bodies of useful trace data. Further, it is important that such a tool will provide such bodies of data in a form easy to analyze at a reasonable cost.
The ability to keep up with the modern high-speed instruction processor makes this particularly challenging, since memory speeds are often far less than the speed with which the processors and processor busses can operate.
Accordingly, there is a need to provide methods and systems for reducing the amount of high speed memory required to capture long traces.
Further, in multiprocessor systems, the interaction between the instruction processors may affect overall system throughput, so analysis of the data of several or all instruction processors on a bus (or other set of interconnections) simultaneously and the ability to match traces generated by each of them becomes important. The ability to capture trace data from different, unconnected processor busses simultaneously is also an important capability lacking in the present state of the art. Thus, a way to keep the trace data effectively organized and matchable with respect to time of generation of each independent instruction processor stream becomes important as well.
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Atlass Michael B.
Iqbal Nadeem
Starr Mark T.
Unisys Corporation
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