Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-01-10
2006-01-10
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S113000, C711S128000, C711S130000, C711S134000, C711S135000, C711S136000
Reexamination Certificate
active
06986001
ABSTRACT:
A system for approximating a least recently used (LRU) algorithm for memory replacement in a cache memory. In one system example, the cache memory comprises memory blocks allocated into sets of N memory blocks. The N memory blocks are allocated as M super-ways of N/M memory blocks where N is greater than M. An index identifies the set of N memory blocks. A super-way hit/replacement tracking state machine tracks hits and replacements to each super-way and maintains state corresponding to an order of hits and replacements for each super-way where the super-ways are ordered from the MRU to the LRU. Storage for the state bits is associated with each index entry where the state bits include code bits associated with a memory block to be replaced within a LRU super-way. LRU logic is coupled to the super-way hit/replacement tracking state machine to select an LRU super-way as a function of the super-way hit and replacement history. Block selection logic then selects a memory block to be replaced within the LRU super-way as a function of predefined selection criteria.
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Sherwood et al., Jun. 30-Jul 4, 2001, pp. 86-97.
Farrokh Hashem
Silicon Graphics Inc.
Sparks Donald
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