Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-12-11
2003-12-30
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S207000, C365S189070
Reexamination Certificate
active
06671218
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuit memories and more specifically to a content addressable integrated circuit memory of the dynamic type in which stored contents expire unless periodically refreshed.
BACKGROUND
Up to the present time, content addressable memories have typically been implemented in static random access memories (SRAMs) rather than dynamic random access memories (DRAMs). SRAMs differ from DRAMs in that they retain stored data indefinitely, so long as power is supplied to the SRAM. By contrast, DRAMs, which have a dynamic type of memory cell (typically consisting of a single transistor and single capacitor), require the stored data therein to be periodically refreshed. Dynamic content addressable memories (DCAMs), like DRAMs, contain a dynamic type of memory cell (a “DCAM cell”) which requires the stored data therein to be periodically refreshed.
Content addressable memories, including DCAMs, permit their stored contents to be searched for an entry that matches a search word presented thereto. To perform a search, a search word is input to each of a plurality of rows of DCAM cells in a DCAM array. If the search word matches an entry stored in any searched row of the DCAM array, a match signal is output for that row. The match signal is then converted to the address of the matching entry for output from the DCAM.
The requirement to periodically refresh the stored data of the DCAM poses a problem. The act of refreshing the data stored within a DCAM cell temporarily destroys the data within that DCAM cell. A refresh operation will read data from a row of DCAM cells into pairs of sense amplifiers. Pairs of sense amplifiers restore data signals received on a true bitline and a complement bitline of each DCAM cell to full voltage levels and then write these signals back to each DCAM cell in the row of DCAM cells to complete the refresh operation. During the time that the data is being read out and written back to a row of DCAM cells, the data is not stored in that row of DCAM cells. At such time, the data is temporarily unavailable to be searched at that row of DCAM cells.
One way to address this problem might be to block searches from being performed on memory arrays that are currently being refreshed, since otherwise the DCAM cannot assure that all entries stored in the memory array are fully searched. However, this is undesirable as it may involve significant delay to wait for all stored entries of the memory array to be refreshed.
SUMMARY
As a way of addressing such problem, the present invention provides a system and method for searching a DCAM which includes comparing search information to the information stored in a plurality of sense amplifiers. Such method includes reading information stored in a row of DCAM cells into sense amplifiers; and comparing search information to the information read into the sense amplifiers to determine if there is a match. Preferably, such method includes restoring the information from the sense amplifiers to the row of DCAM cells. A preferred way of doing the comparison is to apply the search information and the information read into the sense amplifiers to a plurality of match circuits coupled to a match line. The match line then indicates whether there is a match.
In addition, the present invention preferably provides a system and method by which search operations are performed simultaneously with the refreshing of a DCAM array while assuring that all stored entries of the array are searched. In such preferred embodiment, a system and method are provided for simultaneously searching and refreshing a memory array of a dynamic content addressable memory (DCAM). In such way, refresh cycles are hidden within, i.e. performed simultaneously with, search cycles of the DCAM. During a read phase of a refresh operation, the information stored in a row of DCAM cells being refreshed is transferred from the memory array into a row of sense amplifiers. The information transferred to and temporarily stored in the sense amplifiers is then available to be searched. To determine if the DCAM contains a matching entry, a search is performed simultaneously relative to the information temporarily stored in the row of sense amplifiers and to the information stored in other rows of DCAM cells of the memory array. Finally, in a write phase of the refresh operation, the information is rewritten from the sense amplifiers to the row of DCAM cells being refreshed.
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Ashbrook Jonathan B.
Bogaczyk Michael
Chu Albert M.
Gutwin Paul
Hall Ezra
Lebentritt Michael S.
Nguyen Tuan T.
Schnurmann H Daniel
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