System and method for hardware-based GPU paging to system...

Computer graphics processing and selective visual display system – Computer graphics display memory system – Addressing

Reexamination Certificate

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C345S537000, C345S538000, C711S206000, C711S207000

Reexamination Certificate

active

07623134

ABSTRACT:
One embodiment of the present invention sets forth a technique for processing address page requests in a GPU system that is implementing a virtual memory model. A hardware-based page fault manager included in the GPU system intercepts page faults otherwise processed by a software-based page fault manager executing on a host CPU. The hardware-based page fault manager in the GPU includes a DMA engine capable of reading and writing pages between system memory and frame buffer memory without involving the CPU or operating system. A net improvement in system performance is achieved by processing a significant portion of page faults within the GPU, reducing the overall load on the host CPU.

REFERENCES:
patent: 5301287 (1994-04-01), Herrell et al.
patent: 5555395 (1996-09-01), Parks
patent: 5592670 (1997-01-01), Pletcher

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