Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
2006-02-21
2006-02-21
Perveen, Rehana (Department: 2112)
Electrical computers and digital data processing systems: input/
Interrupt processing
C718S102000
Reexamination Certificate
active
07003610
ABSTRACT:
A system and method for handling shared resource writes arriving via non-maskable interrupts in single thread non-mission critical system with limited memory space includes a queue for providing temporary storage of a write request. The queue is accessible by lower or higher priority processes for the servicing of the write requests. Upon completion of service to the write requests the system returns control to the standard operations of the single thread system.
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Lesslie Lance
Owens Jason
Yang Jinchao
LSI Logic Corporation
Perveen Rehana
Suiter - West - Swantz PC LLO
Vu Trisha
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