Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
Reexamination Certificate
2000-04-28
2009-02-24
Li, Aimee J (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Scoreboarding, reservation station, or aliasing
C712S202000
Reexamination Certificate
active
07496734
ABSTRACT:
There is disclosed a data processor comprising 1) a register stack comprising a plurality of architectural registers that stores operands required by instructions executed by the data processor; 2) an instruction execution pipeline comprising N processing stages, where each processing stage performs one of a plurality of execution steps associated with a pending instruction being executed by the instruction execution pipeline; and 3) at least one mapping register associated with at least one of the N processing stages, wherein the at least one mapping register stores mapping data that may be used to determine a physical register associated with an architectural stack register accessed by the pending instruction.
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Huang Lun Bin
Richardson Nicholas J.
Jorgenson Lisa K.
Li Aimee J
Munck William A.
STMicroelectronics Inc.
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