Electrical computers and digital processing systems: processing – Processing control – Processing sequence control
Reexamination Certificate
2006-02-14
2006-02-14
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Processing sequence control
C712S206000, C712S207000, C712S225000, C712S023000, C711S201000, C711S211000
Reexamination Certificate
active
07000097
ABSTRACT:
The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.
REFERENCES:
patent: 4679141 (1987-07-01), Pomerene et al.
patent: 4760519 (1988-07-01), Papworth et al.
patent: 4794517 (1988-12-01), Jones et al.
patent: 4839797 (1989-06-01), Katori et al.
patent: 4901233 (1990-02-01), Liptay
patent: 4916652 (1990-04-01), Schwarz et al.
patent: 4992931 (1991-02-01), Hirasawa
patent: 4992934 (1991-02-01), Portanova et al.
patent: 4992938 (1991-02-01), Cocke et al.
patent: 5003462 (1991-03-01), Blaner et al.
patent: 5051940 (1991-09-01), Vassiliadis et al.
patent: 5075849 (1991-12-01), Kuriyama et al.
patent: 5101341 (1992-03-01), Circello et al.
patent: 5127091 (1992-06-01), Boufarah et al.
patent: 5133072 (1992-07-01), Buzbee
patent: 5133077 (1992-07-01), Karne et al.
patent: 5134561 (1992-07-01), Liptay
patent: 5148528 (1992-09-01), Fite et al.
patent: 5148536 (1992-09-01), Witek et al.
patent: 5155843 (1992-10-01), Stamm et al.
patent: 5168571 (1992-12-01), Hoover et al.
patent: 5185868 (1993-02-01), Tran
patent: 5193206 (1993-03-01), Mills
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5230068 (1993-07-01), Van Dyke et al.
patent: 5233694 (1993-08-01), Hotta et al.
patent: 5247628 (1993-09-01), Grohoski
patent: 5251306 (1993-10-01), Tran
patent: 5261071 (1993-11-01), Lyon
patent: 5276848 (1994-01-01), Gallagher et al.
patent: 5317740 (1994-05-01), Sites
patent: 5323489 (1994-06-01), Bird
patent: 5345569 (1994-09-01), Tran
patent: 5355460 (1994-10-01), Eickemeyer et al.
patent: 5371684 (1994-12-01), Iadonato et al.
patent: 5390355 (1995-02-01), Horst
patent: 5418973 (1995-05-01), Ellis et al.
patent: 5442757 (1995-08-01), McFarland et al.
patent: 5487156 (1996-01-01), Popescu et al.
patent: 5539911 (1996-07-01), Nguyen et al.
patent: 5557763 (1996-09-01), Senter et al.
patent: 5561776 (1996-10-01), Popescu et al.
patent: 5574927 (1996-11-01), Scantlin
patent: 5592636 (1997-01-01), Popescu et al.
patent: 5606676 (1997-02-01), Grochowski et al.
patent: 5619668 (1997-04-01), Zaidi
patent: 5619730 (1997-04-01), Ando
patent: 5625837 (1997-04-01), Popescu et al.
patent: 5627983 (1997-05-01), Popescu et al.
patent: 5651125 (1997-07-01), Witt et al.
patent: 5659782 (1997-08-01), Senter et al.
patent: 5689720 (1997-11-01), Nguyen et al.
patent: 5708841 (1998-01-01), Popescu et al.
patent: 5768575 (1998-06-01), McFarland et al.
patent: 5778210 (1998-07-01), Henstrom et al.
patent: 5797025 (1998-08-01), Popescu et al.
patent: 5832205 (1998-11-01), Kelly et al.
patent: 5832293 (1998-11-01), Popescu et al.
patent: 5930520 (1999-07-01), Ando
patent: 5987593 (1999-11-01), Senter et al.
patent: 6230254 (2001-05-01), Senter et al.
patent: 6434693 (2002-08-01), Senter et al.
patent: 36 03 240 (1987-08-01), None
patent: 0 136 179 (1985-04-01), None
patent: 0 147 775 (1985-07-01), None
patent: 0 170 398 (1986-02-01), None
patent: 0 171 595 (1986-02-01), None
patent: 0 259 095 (1988-03-01), None
patent: 0 259 095 (1988-03-01), None
patent: 0 272 198 (1988-06-01), None
patent: 0 272 198 (1988-06-01), None
patent: 0 302 999 (1989-02-01), None
patent: 0 302 999 (1989-02-01), None
patent: 0 354 585 (1990-02-01), None
patent: 0 354 585 (1990-02-01), None
patent: 0 368 332 (1990-05-01), None
patent: 0 368 332 (1990-05-01), None
patent: 0 372 751 (1990-06-01), None
patent: 0 372 751 (1990-06-01), None
patent: 0 377 990 (1990-07-01), None
patent: 0 377 990 (1990-07-01), None
patent: 0 377 991 (1990-07-01), None
patent: 0 377 991 (1990-07-01), None
patent: 0 380 854 (1990-08-01), None
patent: 0 380 854 (1990-08-01), None
patent: 0 402 856 (1990-12-01), None
patent: 0 402 856 (1990-12-01), None
patent: 0 419 105 (1991-03-01), None
patent: 0 419 105 (1991-03-01), None
patent: 0 426 393 (1991-05-01), None
patent: 0 426 393 (1991-05-01), None
patent: 0 436 092 (1991-07-01), None
patent: 0 436 092 (1991-07-01), None
patent: 0 461 257 (1991-12-01), None
patent: 0 465 321 (1992-01-01), None
patent: 0 465 321 (1992-01-01), None
patent: 0 473 420 (1992-03-01), None
patent: 0 473 420 (1992-03-01), None
patent: 0 479 390 (1992-04-01), None
patent: 0 479 390 (1992-04-01), None
patent: 0 272 198 (1998-06-01), None
patent: 2 575 564 (1986-07-01), None
patent: 2 011 682 (1979-07-01), None
patent: 2 230 116 (1990-10-01), None
patent: 2 241 801 (1991-09-01), None
patent: 58-217054 (1983-12-01), None
patent: 59-154548 (1984-09-01), None
patent: 59-165143 (1984-09-01), None
patent: 61-33546 (1986-02-01), None
patent: 64-86243 (1986-03-01), None
patent: 63-192135 (1988-08-01), None
patent: 64-36336 (1989-02-01), None
patent: 1-286030 (1989-11-01), None
patent: 2-48732 (1990-02-01), None
patent: 2-130634 (1990-05-01), None
patent: 2-148238 (1990-06-01), None
patent: 2-151930 (1990-06-01), None
patent: 4-77925 (1992-03-01), None
patent: 4-153733 (1992-05-01), None
patent: 4-219825 (1992-08-01), None
patent: 8-504977 (1996-05-01), None
patent: 2000-148491 (2000-05-01), None
Tetsuya Hara et al., “Organization of An Extended Superscalar Processor Prototype Based on the SIMP (Single Instruction Stream/Multiple Instruction Pipelining) Architecture”,Electronic Information Communication Society Technical Research Report CPSY90-38-63,Electronic Information Communications Society, Inc., Jul. 20, 1990, vol. 90, No. 144, pp 103-108 (with English language translation, 14 pages).
8-Bit Embedded Controller Handbook,Intel, 1989, pp. 1-1 thru 1-19 and 3-1 thru 3-37.
Acosta, R. D. et al., “An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors,”IEEE Transactions On Computers,IEEE, vol. C-35, No. 9, Sep. 1986, pp. 815-828.
Agerwala, T. and Cocke, J.,A High Performance Reduced Instruction Set Processors,IBM Research Division, Mar. 31, 1987, pp. 1-61.
Aiken, A. and Nicolau, A., “Perfect Pipelining: A New Loop Parallelization Technique*,”ESOP '88, 2nd European Symposium on Programming,Springer, ISBN 3-540-19027-9, 1988, pp. 221-235.
Andrews, W., “Distinctions Blur Between DSP Solutions,”Computer Design,Publisher Unknown, vol. 28, No. 9, May 1, 1989, pp. 86-99.
Bakoglu, H.B. et al., “IBM Second-Generation RISC Machine Organization”,COMPCON Spring 90 digest of papers,IEEE Computer Society, 1990, pp. 173-178.
Charlesworth, A.E., “An Approach to Scientific Array Processing: The Architectural Design of the AP-120B/FPS-164 Family,”Computer,IEEE, vol. 14, Sep. 1981, pp. 18-27.
Colwell, R.P. et al., “A VLIW Architecture for a Trace Scheduling Compiler,”Proceedings of the 2nd International Conference on Architectural Support for Programming Languages and Operating Systems,IEEE Computer Society, Oct. 1987, pp. 180-192.
Crawford, J., “The Execution Pipeline of the Intel i486 CPU,” Publication Source Unknown, IEEE, 1990, pp. 254-258.
Faix, M. and Schuenemann, C., “Combined Macro/Micro Program Machine,”IBM Technical Disclosure Bulletin,IBM, vol. 14, No. 1, Jun. 1971, p. 298.
Foster, C.C. and Riseman, E.M., “Percolation of Code to Enhance Parallel Dispatching and Executio
Senter Cheryl D.
Wang Johannes
Pan Daniel H.
Sterne Kessler Goldstein & Fox PLLC
LandOfFree
System and method for handling load and/or store operations... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for handling load and/or store operations..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for handling load and/or store operations... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3650748