System and method for handling interrupt and exception events in

Details System and method for handling interrupt and exception events in System and method for handling interrupt and exception events in

1996-08-19

1999-12-14

Ramirez, Ellis B.

Electrical computers and digital processing systems: processing

Processing control

Branching

39580028, G06F 1700

Patent

active

060031298

ABSTRACT:
A multiprocessor computer system includes a plurality of processors, called asymmetric processors, having mutually dissimilar control and data-handling characteristics. The asymmetric processors are controlled by a single operating system although the individual processors have instruction sets that are mutually independent of the other processors. The multiprocessor computer system uses a multiprocessor architectural definition of interrupt and exception handling in which a processor, called a data or vector processor, having a large machine state and a large data width detects exceptions but defers interrupt and exception handling operations to another processor, called a control processor, having a small machine state and data width. The small machine state and small data width of the control processor are well suited for executing operating system programs such as interrupt and exception handling since control programs typically involve monitoring and control of individual flags and pointers. The data processor enters an idle state upon reset and when an exception is detected to facilitate system design and programming, and to simplify synchronization of the processors at system reset. A multiprocessor computer system includes a control processor which reads and writes control and status registers within a data processor. The control processor thus controls the operation of the data processor during execution of an operating system or application programs. The control processor has access to the control and status registers of the data processor independent of the data processor execution so that the same control and status registers may be accessed by the control processor and the data processor in parallel.

REFERENCES:
patent: 5193158 (1993-03-01), Kinney et al.
patent: 5278647 (1994-01-01), Hingorani et al.
patent: 5319753 (1994-06-01), MacKenna et al.
patent: 5510842 (1996-04-01), Phillips et al.
patent: 5576765 (1996-11-01), Cheney et al.
patent: 5594905 (1997-01-01), Mital
patent: 5668599 (1997-09-01), Cheney et al.
patent: 5729279 (1998-03-01), Fuller

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