System and method for handling direct memory accesses

Details System and method for handling direct memory accesses System and method for handling direct memory accesses

2003-04-09

2009-12-22

Nguyen, Hiep T (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

07636815

ABSTRACT:
Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known to be safe for external access. If the snoop cache determines that the target address is safe, it signals the external agent to proceed with the direct memory access. If the snoop cache does not determine if the target address is safe, then the snoop cache forwards the request on to the processor. After the processor resolves any coherency problems between itself and the memory system, the processor signals the external agent to proceed with the direct memory access. The snoop cache can determine safe address ranges from such processor activity. The snoop cache invalidates its safe address ranges by observing traffic between the processor and the memory system.

REFERENCES:
patent: 5345576 (1994-09-01), Lee et al.
patent: 5644753 (1997-07-01), Ebrahim et al.
patent: 5704058 (1997-12-01), Derrick et al.
patent: 5761468 (1998-06-01), Emberson
patent: 5860111 (1999-01-01), Martinez et al.
patent: 5897656 (1999-04-01), Vogt et al.
patent: 5953538 (1999-09-01), Duncan et al.
patent: 6088769 (2000-07-01), Luick et al.
patent: 6122714 (2000-09-01), VanDoren et al.
patent: 6128701 (2000-10-01), Malcolm et al.
patent: 6128702 (2000-10-01), Saulsbury et al.
patent: 6205517 (2001-03-01), Sugaya
patent: 6219745 (2001-04-01), Strongin et al.
patent: 6345320 (2002-02-01), Kawamata et al.
patent: 6438653 (2002-08-01), Akashi et al.
patent: 6535960 (2003-03-01), Nishida et al.
patent: 6546464 (2003-04-01), Fortuna et al.
patent: 6633958 (2003-10-01), Passint et al.
patent: 6638653 (2003-10-01), Andou et al.
patent: 6662277 (2003-12-01), Gaither
patent: 6668287 (2003-12-01), Boyle et al.
patent: 6785780 (2004-08-01), Klein et al.
patent: 6868481 (2005-03-01), Gaither et al.
patent: 6925536 (2005-08-01), Glasco et al.
patent: 2003/0005237 (2003-01-01), Dhong et al.
patent: 2003/0131202 (2003-07-01), Khare et al.
patent: 2003/0163745 (2003-08-01), Kardach
Agarwal et al., The MIT Alewife Machine, Mar. 1999, Proceedings of the IEEE, vol. 87, No. 3, pp. 430-444.
Handy, Jim., The Cache Memory Book, 1998, Academic Press, 2ndedition, pp. 155-169.
Jouppi, Norman P., Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers, Proceedings of the 17thAnnual International Symposium on Computer Architecture, at 384-373 (IEEE 1990).
CPU Cache, From Wikipedia, the free encyclopedia Http: //en.wikipedia.org/wiki/CPU. 18 pages. 2009.
Anant Agarwal; et al. “The MIT Alewife Machine”, Laboratory for Computer Science, Massachusetts Institute of Technology Cambridge, Massachusetts, 02139.
Non Final Office Action, Mail Date Apr. 7, 2008;U.S. Appl. No. 11/439,361.
Notice of Allowance, Mail Date Jun. 12, 2009; U.S. Appl. No. 11/439,361.
Notice of Allowance, Mail Date Aug. 26, 2008; U.S. Appl. No. 11/439,361.
Notice of Allowance, Mail Date Dec. 12, 2008; U.S. Appl. No. 11/439,361.
Restriction Requirement, Mail Date Feb. 21, 2008; U.S. Appl. No. 11/439,361.
Final Rejection, Mail Date Feb. 25, 2009; U.S. Appl. No. 11/102,289.
Final Rejection, Mail Date Sep. 28, 2007; U.S. Appl. No. 11/102,289.
Non Final Office Action, Mail Date Mar. 23, 2007; U.S. Appl. No. 11/102,289.
Non Final Office Action, Mail Date May 12, 2009; U.S. Appl. No. 11/102,289.
Non Final Office Action, Mail Date Jun. 12, 2008; U.S. Appl. No. 11/102,289.
Final Rejection, Mail Date Mar. 16, 2009; U.S. Appl. No. 11/102,171.
Final Rejection, Mail Date Nov. 26, 2007; U.S. Appl. No. 11/102,171.
Non Final Office Action, Mail Date Mar. 26, 2007; U.S. Appl. No. 11/102,171.
Non Final Office Action, Mail Date Jul. 09, 2008; U.S. Appl. No. 11/102,171.
Notice of Allowance Dated Mar. 12, 2009; U.S. Appl. No. 11/439,361.
Notice of Allowance Dated Jun. 26, 2009; U.S. Appl. No. 11/439,361.

Affiliated with

Also associated with

Rating

System and method for handling direct memory accesses does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for handling direct memory accesses, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for handling direct memory accesses will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4122825