System and method for half-rate clock phase detection

Details System and method for half-rate clock phase detection System and method for half-rate clock phase detection

2006-09-05

2006-09-05

Fan, Chieh M. (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

Reexamination Certificate

active

07103131

ABSTRACT:
A system and method for half-rate phase detecting are provided. The method comprises: receiving binary data; dividing the data by two; latching the divided data with a first half-rate clock, creating Q1; latching the divided data with a second half-rate clock, the inverse of the first clock, creating Q2; latching Q1with the second clock, creating Q3; latching Q2with the first clock, creating Q4; XORing Q1and Q2to create phase signals; and, XORing Q3and Q4to create reference signals, corresponding to the phase signals. In some aspects of the method, dividing the stream of data by two introduces a processing delay into the divided data. Then, the method further comprises: in response to the phase and reference signals, phase-locking a voltage controlled oscillator to generate the first and second clocks; delaying the received stream of binary data; and, using the first and second clocks to sample the delayed binary data.

REFERENCES:
patent: 6771728 (2004-08-01), Abernathy
patent: 6970020 (2005-11-01), Mei et al.
patent: 2004/0012414 (2004-01-01), Chen et al.

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