Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-01-18
2003-11-18
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06651237
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The field of the present invention relates to electronic design automation and, more particularly, to methods and systems for constructing H-Tree clocking layouts for integrated circuits.
2. Background
Designs of integrated circuits (ICs) can frequently be divided into sub-sections, or blocks, according to functional characteristics, signal characteristics (e.g., analog vs. digital), or other distinguishing features. Moreover, it is increasingly common in chip design to utilize pre-developed “virtual” component blocks, often referred to as Intellectual Properties (IPs) to suggest their proprietary nature, to design complete systems on a chip. Most chip designs require a common clocking signal to be distributed to all of the circuit blocks (or virtual component blocks) of the chip. The clock signal typically enters from a single location (corresponding to a clock I/O pin) of the chip, and is distributed by metal wires from the I/O pad to all of the circuit blocks (or virtual component blocks) requiring use of the clock signal. An ad hoc layout of the clock wires, however, can be disadvantageous, because such a layout generally results in uneven impedance characteristics along the various branches of the clock signal paths. Consequently, different circuit blocks (and virtual component blocks) will receive the same clocking signal at different instants of time, and the clock signal will have different skew characteristics at different circuit blocks (or virtual component blocks). This situation can lead to unsatisfactory chip performance.
One technique that attempts to overcome the problem of uneven impedance characteristics in the different clock signal branches is construction of a balanced H-Tree clock signal layout. In a balanced H-Tree layout, a set of wires for carrying the clock signal is laid out in a tree structure in advance of placement of the circuit blocks (or virtual components). The shape of the clock signal layout is such that each division or split of the clocking signal wire leads into two branches of identical length. The result is that each branch of the clocking signal path has the same impedance characteristics, leading to a balanced clock signal. A drawback of using a conventional balanced H-Tree layout, however, is that the set of wires is fixed prior to placement of the circuit blocks (or virtual component blocks), which can make placement of the circuit blocks (or virtual component blocks) difficult and possibly inconvenient, and sometimes preclude placement of all of the desired circuit blocks (or virtual component blocks).
It would therefore be advantageous to provide a balanced H-Tree layout for a clocking signal which is flexible and does not place undue restrictions on placement of circuit blocks or virtual component blocks, yet provides for an evenly balanced clocking signal.
SUMMARY OF THE INVENTION
The invention provides in one aspect systems and methods for constructing a balanced H-Tree, particularly well suited for application to clock signals in integrated circuits, but applicable to other signals requiring balanced distribution over a wide area as well, in the same or other contexts.
In a preferred embodiment as disclosed herein, a circuit design is provided having a number of circuit blocks in a power of two (preferably sixteen or fewer circuit blocks). The circuit blocks are divided into circuit block groups of equal number (e.g., four). An upper H-Tree clock structure is established using the center of mass of each of the circuit block groups as guideposts, and making adjustments in wire length to balance the H-Tree. A lower H-Tree clock structure is established using center points between pairs of adjacent or nearby circuit blocks as guideposts for the endpoints of clock wires, and then routing, if necessary, wire segments to the individual circuit blocks.
Further embodiments, modifications, variations and enhancements are also described herein.
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Cooke Laurence H.
Venkatramani Kumar
Bingham & McCutchen LLP
Cadence Design Systems Inc.
Siek Vuthe
Tat Binh C.
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