Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-06-20
2006-06-20
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07065726
ABSTRACT:
The present invention is used for guiding formal verification of a circuit design in circuit simulation software to optimize the time required for verification of a circuit design. The invention modifies the analysis region being used for verification in order to optimize the time for verification. The invention allows for manual, semi-automatic, and automatic modification of the analysis region. The modification is done by either expanding or reducing the analysis region or by adding new rules as assumptions to the existing analysis region. The invention also uses the concept of an articulation point for modification of the analysis region. The modification of the analysis region is performed in a manner to optimize time and memory required for verification of the circuit design.
REFERENCES:
patent: 5483470 (1996-01-01), Alur et al.
patent: 6099575 (2000-08-01), Hardin et al.
patent: 6449750 (2002-09-01), Tsuchiya
patent: 2003/0115562 (2003-06-01), Martin et al.
patent: 2003/0208730 (2003-11-01), Singhal et al.
R.E. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation”, IEEE Transactions on Computers, vol. C-35, No. 8, Aug. 1986.
Dong Wang et al., “Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines”, Carnegie Mellon University, Design Automation Conference 2001.
C. Kern et al., “Formal Verification in Harware Design: A survey”, ACM Trans. on Design Automtion of Electronic Systems, vol. 4, No. 2, Apr. 1999, p. 123-193.
Higgins Joseph E.
Ip Chung-Wah Norris
Singhal Vigyan
Wong-Toi Howard
Fenwick & West LLP
Jasper Design Automation, Inc.
To Tuyen
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