Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-05-22
2007-05-22
Sough, Hyung (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S158000, C711S168000, C710S244000, C718S102000, C718S103000, C718S107000
Reexamination Certificate
active
10277602
ABSTRACT:
A scheduler may be configured to schedule a plurality of blocks of concurrent code for multi-threaded execution. The scheduler may be configured to initiate multi-threaded execution of the blocks of concurrent code in an order determined by block-level performance criteria for the blocks of concurrent code to reduce overall execution time of the concurrent code. In one embodiment, the scheduler may be configured to schedule code blocks having a longer run time ahead of blocks having a shorter run time. The scheduler may be configured to schedule a group of said blocks based on a goal of each of the blocks of the group completing execution at approximately the same time. The scheduler may also be configured to initiate multi-threaded execution of each block of the group at different times according to the block-level performance criteria to the goal.
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Dutt Bala
Kumar Ajay
Susarla Hanumantha R.
Chery Mardochee
Kowert Robert C.
Meyertons, Hood, Kivlin, Kowert & Goetzel P.c.
Sough Hyung
Sun Microsystems Inc.
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