Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Reexamination Certificate
2000-03-17
2001-05-22
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
C711S218000, C711S220000, C711S212000
Reexamination Certificate
active
06237075
ABSTRACT:
BACKGROUND OF THE INVENTION
Code generators are used in many areas of electronics. The most common generators consist of a serial-input, parallel-output shift register with selected outputs being exclusive-or'd and fed back to the data input of the shift register. These codes are limited and only minimally arbitrary and provide no flexibility for selecting alternative codes or varying phases of one code. These drawbacks are exacerbated, since most of these circuits are hardwired.
As noted, most code generators of this type are restricted to a single code. A primary concern with code generators is avoiding loading all zeros in the code generator; thereby, causing the code generator to cease operation. These types of code generators are often used to generate maximal-length linear codes for direct sequence spread spectrum communication systems. They may be used to test communication lines and as building blocks in stream ciphers. These codes are typically equal to 2
N−1
, where N is equal to the number of shift registers. As an example, an 8 bit shift register is capable of generating one of 16 possible 255-bit codes. The code is a function of the selected feedback outputs.
Random access memory (RAM) and read-only memory (ROM) have been used to store arbitrary codes and they are immune to situations resulting in the shift register having all zeros. Typically, the memory is addressed by an address counter, which must be reset at the end of the code. Resetting this counter requires a means to determine that the end of the code has been reached and means to reset the address counter accordingly. Furthermore, a data latch is required to latch the data from the memory to avoid an erroneous output due to settling after inputs to the address line are changed. Since most memory provides a parallel eight-bit wide data output and the required code is serial, most memory-based code generators either output eight different codes simultaneously, which requires further logic to select the required code, or store eight bits of the code per byte, which requires circuitry adapted to load the eight bits into a parallel-input to serial-output shift register and clock the register contents serially. The latter configuration requires two clocks running at different frequencies. As is easily seen, such a circuit becomes very complex and expensive due to the large number of circuit elements.
Thus, there is a need for an inexpensive way to generate any required pseudo-random or arbitrary code. The means should avoid ceasing operation due to an all-zero condition in the shift registers and avoid requiring an address counter to access the code. Furthermore, there is a need for a means to generate and select multiple codes and/or different phases thereof in a simple and inexpensive manner.
SUMMARY OF THE INVENTION
The present invention eliminates all of the undesired features of the above systems and provides an inexpensive solution requiring only two components and a clocking signal. The invention provides either random access or a read-only memory and a latching circuit wherein data held in a first memory location is used to address the next memory location, in addition to providing a synchronous portion of the code.
Accordingly, the data at the next memory address is used as a succeeding address and a subsequent portion of the code. The data is organized to repeat when the data stored in the address location is equal to the starting address. Accordingly, the present invention provides a pseudo-random code generator including a memory having multiple uniquely addressable memory locations, address inputs for selecting any one of the memory locations, and data outputs providing data stored in an addressed memory location. Latch circuitry is included and adapted to provide a latch output of a latch input upon receiving a clock signal. At least part of the data output is coupled to a latch input, and at least part of the latch output is coupled to the address input. A portion of the data from any one memory location latched at the last output represents at least part of an address for an immediately succeeding one of said memory locations to be addressed and a portion of a pseudo-random code. When the latching circuitry is continuously clocked, at least part of an address for the immediately succeeding memory location and a pseudo-random code is formed from a portion of the latched outputs.
The pseudo-random code may be provided by at least one of the latched outputs wherein each latched bit at the corresponding latch output is one bit of the pseudo-random code. Each portion or bit may also represent one bit of different codes or different phases of the same code. Preferably, the data is configured to provide pseudo-random codes in a maximal length linear code format for use in spread spectrum communications.
These and other aspects of the present invention will become apparent to those skilled in the art after a reading of the following description of the preferred embodiments when considered in conjunction with the drawings.
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Abbat Pierre Henri Michel
Emery David L.
Kim Matthew
Pan Atlantic Corporation
Peugh Brian R.
Withrow & Terranova, P.L.L.C.
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