System and method for generating pseudo-random codes

Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses

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711218, 711220, G06F 1200

Patent

active

060790075

ABSTRACT:
The invention provides a read-only memory and a latching circuit wherein data held in a first memory location is used to address the next memory location, in addition to providing a synchronous portion of the code. Accordingly, the data at the next memory address is used as a succeeding address and a subsequent portion of the code. The data is organized to repeat when the data stored in the address location is equal to the starting address.

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