Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2004-07-16
2008-11-11
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Branching
Reexamination Certificate
active
07451299
ABSTRACT:
State machines can be used in a scanner and a parser for program compilation. The state machines can be non-table-driven, but rather are encoded directly in bytecodes. A special algorithm can be used to generate the multi-way branch associated with a state in a state machine so that the multi-way branch meets specified optimality requirements on the size of the bytecodes. The bytecodes so implemented can be more compact and run faster than those generated un-optimized. The algorithm for obtaining an optimal implementation of the multi-way branch can be conceptually divided into three phases: first, it constructs a set of subarrays that form a disjoint covering for the target array; second, it determines an optimal branch implementation for each subarray; and third, it determines the optimal branch implementation for each union of one or more adjacent subarrays, culminating to the optimal implementation for the entire target array. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures, and the claims.
REFERENCES:
patent: 5339420 (1994-08-01), Hoxey
patent: 5995963 (1999-11-01), Nanba et al.
patent: 6272641 (2001-08-01), Ji
patent: 6301703 (2001-10-01), Shank et al.
patent: 6327704 (2001-12-01), Mattson, Jr. et al.
patent: 6536031 (2003-03-01), Ito et al.
patent: 6598225 (2003-07-01), Curtis et al.
patent: 6775763 (2004-08-01), Sexton et al.
patent: 6993706 (2006-01-01), Cook
patent: 7062728 (2006-06-01), Tojima
patent: 2002/0184479 (2002-12-01), Sexton et al.
A hybrid state machine notation for component specification, Apr. 2000, ACM vol. 35, issue 4.
Algorithms in Java, Jul. 2002, Addison Wesley Professional, 3rdEd. section 5.2, chapters 12 and 15.
J.Shirazi, Java Performance Tuning, 2000,O'Reilly, 1stEd., pp. 189-195.
McEnerney John
Zatloukal Kevin
BEA Systems Inc.
Coleman Eric
Fliesler & Meyer LLP
LandOfFree
System and method for generating multi-way branches does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for generating multi-way branches, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for generating multi-way branches will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4024001