Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1998-10-01
2001-02-20
Tu, Christine T. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S758000
Reexamination Certificate
active
06192498
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
TECHNICAL FIELD
The present invention relates to the field of data communications, and more particularly, to the field of framing data in a communications system.
BACKGROUND INFORMATION
In data communications, data is generally transmitted in a bit-serial communications format through current networks. It is often the case that the data to be transmitted between two data endpoints is packaged according to specific data communications protocols to facilitate the transmission across the particular network in question. This packaging may include the addition of network management and other information such as headers and trailers to the data to facilitate transmission based upon the dictates of the particular protocol employed. Such packaging is generally termed “framing” in the art.
Some of these protocols may include, for example, data transmission using time division multiplexing (TDM) approaches such T1 and E1 standards known in the art. Other example standards may include high-level data link control (HDLC) or asynchronous transfer mode (ATM). Each of these protocols have their own applications and goals in terms of history, performance, error-immunity, flexibility, and other factors. Consequently, each of these protocols employ framing procedures by which data is packaged for transmission across the various networks employed. These protocols are generally incompatible and require translation or conversion to transmit data in a transmission link that employs two or more protocols in two or more different segments.
The conversion from one protocol to another requires specific framing technology to accomplish the task. With a myriad of standards between which conversion is possible, many different dedicated protocol conversion units have been developed to accomplish the specific conversion tasks presented. The typical protocol conversion unit is labeled “dedicated” above because such units generally employ dedicated circuits which are capable only of performing the conversion from one specific protocol to another. The result of this fact is a multitude of protocol conversion units on the market to accomplish the individual conversion tasks, thereby diminishing efficiencies to be obtained by mass production.
It is also the case that new communications standards are developed as data communication technology develops over time. Often times, a particular standard may be in flux while discussion ensues among those skilled in the art until agreement on concrete provisions articulating a standard is reached. Consequently, it is difficult to develop data communications technology that employs an up and coming standard until the standard is settled. In the competitive world of data communications technology production, it is desirable to produce products to meet these new standards as quickly as is possible after a standard is finalized so as to compete in the marketplace.
BRIEF SUMMARY OF THE INVENTION
In light of the foregoing, it is an objective of the present invention to provide for technology which can achieve protocol conversions between any number of protocols to obtain the efficiencies of mass production and feature the flexibility allowing the unit to be quickly adapted to new data communications protocols as they develop. In addition, there is a corresponding objective to provide for circuits which can perform specific tasks in conjunction with the aforementioned protocol conversions, such as, for example, a circuit to generate cyclic redundancy check data information.
In furtherance of these and other objectives, the present invention entails a circuit and method for generating cyclic redundancy check (CRC) data. In one embodiment, the circuit interfaces with a data bus and other processor components. The circuit includes an input first-in-first-out (FIFO) to interface with the data bus, a configuration register electrically coupled to the data bus, and a configurable CRC generation circuit electrically coupled to the data bus and to the configuration register. The CRC generation circuit includes a bit shift register which is configurable to generate CRC data for multiple protocols. To accomplish this, the bit shift register is configurable for different lengths, the actual length of the bit shift register being determined by the data communication protocols employed. The bit shift register also features multiple inputs to allow the CRC generation circuit to employ any CRC generation polynomial based on the data communications protocols. The CRC generation circuit also provides and additional advantage in that the bit shift register can be configured into multiple registers to use in ATM signal synchronization.
The present invention may also be viewed as a method for generating CRC data which comprises the steps of receiving a data input from a data bus, generating a CRC configuration control signal based upon the data input using a predetermined data communications protocol, and generating CRC data based upon the CRC configuration control signal, the CRC data being transmitted to the data bus.
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patent: 5671237 (1997-09-01), Zook
patent: 5870413 (1999-02-01), Kodama et al.
Al Chamé, “Applications Information Interfacing the 68360 (QUICC) to T1/E1 Systems,” Motorola Semi-conductor Technical Information, pp. 1-18, 1993.
“Communications Processor Module (CPM),” Motorola MC68360 Quad Integrated Communications Controller User's Manual, rev. 1, ch. 7, Dec. 4, 1996, pp. 7-1-7-381.
Globepan, Inc.
Thomas Kayden Horstemeyer & Risley
Tu Christine T.
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