Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-11-02
2010-12-21
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07856607
ABSTRACT:
A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern.
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Grise Gary D.
Habitz Peter A.
Iyengar Vikram
Lackey David E.
Visweswariah Chandramouli
Downs Rachlin & Martin PLLC
International Business Machines - Corporation
Siek Vuthe
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