Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-08-11
2001-07-17
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06263478
ABSTRACT:
FIELD OF INVENTION
This invention pertains to the fields of generating and using constraints for timing-driven design of integrated circuits. More particularly, this invention relates to the generation and use of stage-based constraints for timing-driven design of integrated circuits.
BACKGROUND OF INVENTION
Traditional methods for specifying the timing constraints on an integrated circuit design fall into two categories: system level constraints entered by the user, and detailed path constraints generated automatically from the system level constraints. System level constraints are very compact and provide full coverage of the timing constraints on the entire design, but they require complicated timing analysis techniques to interpret accurately. Detailed path constraints are straightforward to interpret, and have therefore been used extensively in timing-driven placement and routing tools. However, the number of detailed path constraints required to provide reasonable coverage makes this approach unsuitable for very large designs. To address this problem, this invention defines a new formulation of timing constraints, which provides a compact representation with no loss of the information in system level constraints, yet is simple and efficient to interpret. Mechanisms for automatically generating these stage-based constraints are described, along with the use of the constraints for timing-driven placement, timing-driven routing, and incremental logic optimization.
As circuit density increases, deep-submicron effects on the ratio between interconnect delay and gate delays become increasingly important. These effects make it necessary to perform timing-driven placement, physically-based incremental logic optimization, and timing-driven routing.
Although existing techniques for passing timing constraints to placement and routing are well-established, we expect that in the near future these techniques will reach their limits in performance and capacity. As designs of more than a million gates become common-place, the traditional approach based on detailed path constraints will run into problems with the amount of time required to generate the constraints, the file size needed to pass them from tool to tool, and the memory usage and CPU time required to interpret them.
Worse, each of the existing techniques for generating detailed path constraints suffers from a lack of coverage. Some paths in the design go unconstrained, often because the number of path constraints is restricted to reduce their size, but also because the mechanisms for selecting the paths do not ensure that every path in the design is covered. One popular path selection technique, used in the Synopsys Design Compiler “cover_design” method of generating detailed path constraints, still suffers from a coverage problem for paths through reconvergent logic.
Because of this lack of coverage, detailed path constraints are not suitable for driving incremental logic optimization.
SUMMARY OF THE INVENTION
An integrated circuit design is divided into partitions which each contain two stages of information. The first stage corresponds to sources within the design, and the second stage corresponds to targets within the design. A source is associated with an arrival time of a specific clock edge which triggers that source. A target is associated with a required departure time for a specific clock edge which triggers that target. In one implementation, all of the sources in each partition are triggered by a common clock edge. In another implementation, all of the targets in each partition are triggered by a common clock edge. Both of these implementations includes two sub-implementations. For the implementation in which all sources are triggered by a common clock edge, there is one sub-implementation in which all targets in each partition are also triggered by a common clock edge, and another sub-implementation in which this is not true. Similarly, for the implementation in which all targets are triggered by a common clock edge, there is one sub-implementation in which all sources in each partition are also triggered by a common clock edge, and another sub-implementation in which this is not true. The partitions can be used to determine how much slack, if any, is present in a design.
Each partition groups together paths which share a similar cycle accounting. By minimizing the amount of information in each partition, a timing analysis which covers all possible paths is possible for a large design without requiring enormous amounts of storage for constraint files.
REFERENCES:
patent: 5095454 (1992-03-01), Huang
patent: 5251147 (1993-10-01), Finnerty
patent: 5452239 (1995-09-01), Dai et al.
patent: 5550748 (1996-08-01), Xiong
patent: 5650938 (1997-07-01), Bootehsaz et al.
patent: 5778216 (1998-07-01), Venkatesh
patent: 5825658 (1998-10-01), Ginetti et al.
Hauge, Peter S., Nair, Ravi, Yoffa, Ellen J., “Circuit Placement for Predictable Performance”, Digest of Technical Papers, pp. 88-91, IEEE International Conference on Computer-Aided Design ICCAD-87, Nov. 9-12, 1987, Santa Clara, California.
Cadence Design Systems, Inc., “General Constraints Format Specification”, Version 1.2, Aug. 22, 1997, San Jose, California.
Frankle, Jon, “Iterative and Adaptive Slack Allocation for Performance-Driven Layout and FPGA Routing” Paper 34.1, pp. 536-542, 29thACM/IEEE Design Automation Conference Proceedings 1992, Jun. 8-12, 1992, Anaheim, California.
Hitchcock Sr., Robert B., Smith, Gordon L., Cheng, David D., “Timing Analysis of Computer Hardware”, IBM J. Res. Develop., vol. 26, No. 1, pp. 100-105, Jan. 1982, Endicott, New York.
McWilliams, Thomas M., “Verification of Timing Constraints on Large Digital Systems”, pp. 139-147, 17thDesign Automation Conference Proceedings, Jun. 23-25, 1980, Minneapolis Minnesota.
Youssef, Habib, Shragowitz, Eugene, “Timing Constraints for Correct Performance”, Digest of Technical Papers, pp. 24-27, IEEE International Conference on Computer-Aided Design ICCAD-90, Nov. 11-15, 1990, Santa Clara, California.
Hahn Mark S.
He Limin
Lam Jimmy
Morrison Chris
Cadence Design Systems Inc.
Do Thuan
Lyon & Lyon LLP
Smith Matthew
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