Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-12-30
2008-12-30
Lin, Sun J (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07472361
ABSTRACT:
A method of producing multiple models of a hardware (integrated circuit) design including: translating a master model of a design of the integrated circuit to at least first and second models that are functionally equivalent to the master model and that are at different levels of abstraction from each, other and in which each of the first and second models includes integrated circuit timing information that is accurate for its level of abstraction.
REFERENCES:
patent: 5903466 (1999-05-01), Beausang et al.
patent: 6169968 (2001-01-01), Kabuo
patent: 6182258 (2001-01-01), Hollander
patent: 6779163 (2004-08-01), Bednar et al.
patent: 6820240 (2004-11-01), Bednar et al.
patent: 6883152 (2005-04-01), Bednar et al.
patent: 2005/0149898 (2005-07-01), Hakewill et al.
patent: 2007/0067751 (2007-03-01), Seno
Cesario et al., “Efficient Integration of Behavioral Synthesis within Existing Design Flows”, Sep. 2000, IEEE 13thInternational Symposium on System Synthesis, Proceddings, pp. 85-90.
Calazans et al., “From VHDL Register Transfer Level to SystemC Tranaction Level Modeling: A Comparative Case Study”, Sep. 2003, IEEE 16thIntegrated Circuits and System Design, Proceedings, pp. 355-360.
Cai et al.,“Transaction Level Modeling: An Overview”, Oct. 2003, ACM, pp. 19-24.
Hardee,“Transaction-Level Modeling and ConvergenSC Products”, 2003, coWareInc, paper 6 pages.
Punkka,“SystemC System-Level Modeling”, 2004, Tampere University of Technology, technology presentation slides, 10 pages.
Rissa et al.,“Evaluation of SystemC Modeling of Reconfigurable Embedded System”, 2005, Design, Automation and Test in Europe amd Exhibition, Proceddings, vol. 3, pp. 253-258.
U.S. Appl. No. 11/324,004, filed Dec. 30, 2005, Knapp et al.
U.S. Appl. No. 11/324,032, filed Dec. 30, 2005, Watanabe et al.
U.S. Appl. No. 11/324,169, filed Dec. 30, 2005, McNamara.
Kondratyev Alex
Lavagno Luciano
Watanabe Yosinori
Cadence Design Systems Inc.
Duane Morris LLP
Durant Stephen C.
Lin Sun J
LandOfFree
System and method for generating a plurality of models at... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for generating a plurality of models at..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for generating a plurality of models at... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4036647