Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-07-09
2002-09-17
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C700S121000, C700S120000, C700S098000, C430S005000, C378S035000
Reexamination Certificate
active
06453458
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates generally to photolithography, and more particularly, to a system and method for mapping a two-dimensional flat grid design to a special mask design for further projection onto a three-dimensional object.
Conventional integrated circuits, or “chips,” are formed from two dimensional or flat surface semiconductor wafers. The semiconductor wafer is first manufactured in a semiconductor material manufacturing facility and is then provided to a fabrication facility. At the latter facility, several layers are processed onto the semiconductor wafer surface using various design concepts, such as very large scale integrated (“VLSI”) design. Although the processed chip includes several layers of materials fabricated thereon, the chip still remains relatively flat.
One of the most important steps of manufacturing the chip is to process the semiconductor substrate through a series of photo lithographical processes so that the VLSI design can be transferred to the relative flat plane of the wafer. Since the VLSI design normally defines the entire circuit design, including different layers of materials such as poly, metal, etc., a plurality of photo masks must be made to facilitate the photolithography for each of those layers. In a conventional mask design process, it is conventional to project the pattern for each layer of material of the entire circuit to a flat glass mask, usually in a rectangular shape. Although several intermediate technical steps are involved, the making of the mask is a straightforward one-to-one projection from the VLSI design to the glass. In other words, the VLSI design is directly projected to the mask.
In U.S. Pat. No. 5,955,776 filed on May 16, 1997, a method and apparatus for manufacturing spherical-shaped semiconductor integrated circuit devices is disclosed. The above patent describes and teaches certain methods for performing photolithography on a spherical substrate.
However, there are numerous problems associated with imaging a two-dimensional circuit design to a three-dimensional object, such as a sphere. Since the circuit design on the mask is projected on the sphere, a conventional mask produced directly from the circuit design does not work well. For example, a rectangular entity on the VLSI design can not maintain its shape while it is projected on the sphere. Thus, direct projection from the VLSI design to the glass mask can no longer be used. A new type of mask design is needed to accommodate the need of producing the circuit on the sphere.
Therefore, what is needed is a system and method for mapping a conventional circuit design onto a special mask for projection onto a three-dimensional surface such as a spherical shaped semiconductor device.
SUMMARY OF THE INVENTION
The present invention, accordingly, provides a system and method for mapping a two-dimensional circuit pattern to a flat mask, which is further projected onto a three dimensional substrate. To this end, one embodiment of the method generates a mask containing a conventional circuit pattern for projection onto a surface of a spherical semiconductor device. The circuit pattern is separated into a plurality of circuit segments, so that each circuit segment is enclosed in a polygonal shape. The circuit segments are then mapped into mask segments. And the boundary conditions for each of the mask segments are adjusted to prevent unnecessary overlapping at boundaries of the projected image on the sphere.
In one embodiment of the invention, the mask has a plurality of radially concentric circular orbits wherein the mapped circuit segments, referred to as mask segments, reside.
An advantage of the present invention is that the mask remains two-dimensional. Therefore, the mask can be made like any conventional mask using the conventional mask making tools.
Another advantage of the present invention is that the circuit pattern can be completed using conventional design tools without excessive concerns about having the circuit design being implemented on a three dimensional surface instead of a flat surface.
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Feng Zhiqiang
Fukano Atsuyuki
Koide Hideki
Ball Semiconductor Inc.
Haynes and Boone LLP
Kik Phallaka
Smith Matthew
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