Computer graphics processing and selective visual display system – Computer graphics display memory system – Addressing
Reexamination Certificate
1999-01-27
2001-11-27
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Addressing
C345S556000
Reexamination Certificate
active
06323868
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to improvements in memory addressing, and relates more specifically to a system and method for frame and field memory access operations within a wide-word memory.
2. Description of the Background Art
Controllers for digital audio and digital video information must rapidly manipulate substantial amounts of data. A common architectural approach to facilitate this data manipulation is to organize the memory so that it transfers the data in wide words. In this manner, many bytes of data may be transferred simultaneously during a single memory access. It is desirable for direct memory access (DMA) transfers to be organized to allow multiple wide-word transfers with little intervention from functional units processing the digital audio and video.
One common format for storing and presenting digital audio and video information is Moving Picture Experts Group version 2 (MPEG-2). MPEG-2 has been chosen as the video format for digital video disks (DVD) and digital television (DTV). The MPEG-2 format achieves substantial data compression by recognizing the existence of spatial and temporal redundancy in moving pictures, and then omitting these redundant elements. Spatial redundancy is reduced by a process that includes performing a discrete cosine transform on a matrix of adjacent picture elements (pixels). The MPEG-2 specification has standardized the size of this matrix as 8-by-8 pixels, and named this matrix a “block”. An MPEG-2 block should not be confused with an MPEG-2 “macroblock” used to reduce temporal redundancy. Because of the defined blocks in MPEG-2, manipulating arrays of data in memory corresponding to these blocks is an important consideration in digital video controllers for MPEG-2-formatted video.
A controller for MPEG-2 video on a DVD has an additional concern. A DVD player may be connected to either an interlaced or a non-interlaced (progressive-scan) video display. An interlaced video display shows two alternating fields of display lines, odd and even, to produce a single frame of video. A progressive-scan video display shows a single frame of consecutive display lines. An example of an interlaced video display is a standard analog television set, and an example of a progressive-scan video display is a computer display monitor. A recorded DVD disk may need to be displayed on either an interlaced or a progressive-scan display. For this reason, it may be necessary for a controller of MPEG-2 video on a DVD to rapidly convert digital data organized by frames (for progressive-scan displays) into digital data organized by fields (for interlaced displays). Therefore, techniques for rapidly manipulating substantial amounts of data remain a significant consideration in memory addressing operations.
SUMMARY OF THE INVENTION
The present invention comprises an efficient system and method for reading and writing data from memory which is organized to represent either field or frame video data in a wide-word configured memory. In one embodiment, a memory controller is configured to read or write either sequential wide-words or alternate wide-words in a direct-memory-access (DMA) transfer as directed by software. After the DMA transfer is initiated, the memory read or write operations proceed automatically until the DMA transfer is completed. The ability to read or write either sequential or alternate wide-words beneficially supports operations to convert between field video data for interlaced video displays and frame video data for progressive-scan displays.
In one embodiment of the present invention, a DMA transfer reads data from synchronous-dynamic-random-access-memory (SDRAM) and places the data into a video post-process filter within a controller for digital video disk (DVD) or digital video broadcast (DVB). A reduced-instruction-set-computer (RISC) central-processing-unit (CPU) within the controller preferably initiates a DMA transfer to the video post-processing filter by sending a 32-bit address to a memory arbitrator within a memory controller of the controller. Then a memory address generator within the memory controller generates a first individual address based upon contents of a dynamic-random-access-memory byte address (DBA) contained within the 32-bit address. An SDRAM interface within the memory controller asserts the individual address generated by the memory address generator and sends a wide-word containing a byte addressed by the individual address to the video post-processing filter.
The memory address generator then determines whether there are any additional wide-words to be transferred in the present DMA transfer by testing whether a byte count field is exhausted. If so, then the DMA transfer is complete. Conversely, if the byte count field is not exhausted, then the memory address generator similarly calculates a next individual address.
The memory address generator determines whether a current DMA transfer is of frame type or field type by testing whether a flag bit of 32-bit address equals 0. If so, then the DMA transfer is of field type, and the memory address generator therefore adds 10 hexadecimal to the current contents of the DBA. Conversely, if the flag bit equals 1, then the DMA transfer is of frame type, and the memory address generator therefore adds 08 hexadecimal to the current contents of the DBA. In either case, the memory address generator decrements the byte count field.
After the memory address generator has calculated the next individual address, the SDRAM interface again asserts an individual address and sends a wide-word containing a byte addressed by the individual address to the video post-processing filter. This process of generating individual addresses and reading from memory continues until the memory address generator determines that the byte count field is exhausted and thus that there are no additional wide-words to be transferred in the current DMA transfer.
The process described above applies equally for a memory write DMA transfer if the foregoing step describing a memory read is replaced with a similar step describing a memory write to a wide-word containing a byte addressed by an individual address from the video post-processing filter.
The present invention therefore provides a system and method for frame and field memory read and write operations within a wide-word organized memory.
REFERENCES:
patent: 5241663 (1993-08-01), Rohwer
patent: 5577228 (1996-11-01), Banerjee et al.
patent: 5619282 (1997-04-01), Song
patent: 5708849 (1998-01-01), Coke et al.
patent: 5854651 (1998-12-01), Howard et al.
patent: 5999693 (1999-12-01), Juri et al.
Lin Kuei-Cheng
Paluch, Jr. Edward John
Koerner Gregory J.
Simon & Koerner LLP
Sony Corporation
Tung Kee M.
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