System and method for forward error correction

Details System and method for forward error correction System and method for forward error correction

2003-03-13

2009-06-09

Chaudry, Mujtaba K. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S762000

Reexamination Certificate

active

07546516

ABSTRACT:
Prior to transmission, data bits are arranged into matrices having blocks sized in accordance with a size or rate of an error burst. The matrices are arranged into an ordered set having first and second dimensions. One or more sets of check bits are generated for each block of data bits. At least one set of first check bits relates to the first dimension, and at least one set of second check bits relates to said second dimension. The ordered set of matrices is transmitted across a transmission channel and received at a decoder-corrector. One or more errors in data bits of the ordered set of matrices are detected and corrected, by the decoder-corrector, based on the check bits.

REFERENCES:
patent: 4556960 (1985-12-01), Cohn et al.
patent: 4665537 (1987-05-01), Moriyama
patent: 5708667 (1998-01-01), Hayashi
patent: 5751740 (1998-05-01), Helbig, Sr.

Affiliated with

Also associated with

Rating

System and method for forward error correction does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for forward error correction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for forward error correction will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4145031