Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2001-03-21
2004-05-25
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S701000
Reexamination Certificate
active
06742155
ABSTRACT:
The following invention relates generally to the field of communication systems, and specifically a system and method for Forward Error Correction (FEC) in such systems.
BACKGROUND OF THE INVENTION
Forward Error Correction (FEC) is commonly used in communications systems to improve noise immunity and decrease the Bit Error Rate (BER).
FIG. 1
illustrates a typical FEC implementation, represented generally by the numeral
10
. FEC is typically achieved through the use of an encoder
12
in a transmitter
14
and a decoder
16
in a receiver
18
. The purpose of the FEC encoder
12
is to add redundancy to the data stream at the transmitter
14
. The FEC decoder
16
uses this knowledge at the receiver to detect and correct any transmission errors.
The area of FEC encoding has seen much research and, as a result, there exist a number of different types and classes of FEC codes. Block codes are one such class that is common in communication applications. These codes are characterized by the addition of R check bytes to each block of K information bytes. FEC block codes are designed and characterized to correct a specified number of errors within a data block of a given size. The number of errors that can be corrected depends on the number of inserted check bytes and defines the error correcting capacity of the code.
In order to increase the system's noise immunity to burst errors larger than the FEC code's correcting capacity, a technique known as interleaving is often employed in conjunction with the encoder and decoder. The purpose of interleaving is to reorder the transmitted bytes and shuffle the data over multiple codewords prior to transmission. The bytes are shuffled by an interleaver
20
. At the receiver, the data is reassembled into its original order by a deinterleaver
22
prior to further processing.
The objective of interleaving on burst errors is to partition the burst into pieces and distribute the errors across multiple codewords. As long as the number of errors introduced to each codeword is smaller than the error correcting capacity of the codeword, then the decoder can correct all of the errors in the corrupted burst. This may be true even if the total size of the corrupted burst exceeds the error correcting capacity of a single codeword.
Typically, interleaving blocks are implemented with RAM and the interleaver and deinterleaver simply generate the read and write address control. The interleaver generates the write address for the RAM and interleaves the data as it is written into the RAM, while the deinterleaver generates the read address and deinterleaves the received data as it is extracted from the RAM.
FIG. 2
exemplifies the performance of the interleaver
20
and deinterleaver
22
. In this example, the FEC codewords are convolutionally interleaved by delaying the i-th codeword byte by (D−1)×i bytes, where D is the programmable interleaving depth. The deinterleaver performs the reverse operation (that is, delays the i-th codeword byte by (D−1)×(N−i) bytes, where N is the codeword length). Convolutional interleaving implies that as the k-th codeword is being transmitted, the (k-(D−1))th codeword is being received. This is the interleaving specification for G.992.2 compliant Digital Subscriber Loop (DSL) systems.
In the particular example of
FIG. 2
, N=5 and D=2. Therefore, for the input data stream DATA_IN, the first N (five) codeword bytes B
0
k
through B
4
k
(i.e., the k-th codeword Bx
k
) become the first, third, fifth, seventh and eleventh codeword bytes of the transmitted data stream ILV DATA. The preceding N codeword bytes B
0
k−1
through B
4
k−1
(i.e., the (k−1)th codeword Bx
k−1
) of the input data stream do not appear in the illustrated portion of DATA_IN but as they have been similarly delayed, the last two (B
3
k−1
and B
4
k−1
) appear as the second and fourth codeword bytes of ILV DATA. Thus, as the k-th codeword Bx
k
is being transmitted, the (k−1)th codeword Bx
k−1
is being received.
To process a single stream of data, the RAM requirement for each of the interleaver and deinterleaver blocks is given by D×N bytes. Thus, at any instant, a quantity of RAM buffers equal to D separate FEC codewords.
It is typical to implement the interleaving and coding functions separately, including any necessary buffering, as shown in FIG.
1
. The decoder
16
requires enough buffer memory to store a single FEC codeword, while the interleaver
20
and deinterleaver
22
require enough memory to store D codewords.
One of the greatest challenges facing those implementing DSL systems today is how to reduce the size of their product as well as the amount of power it consumes. However, implementing the FEC system requires both area to implement the system, as well as power to drive it. Therefore, what is needed is a device that can perform FEC while occupying less space and using less power than current implementations.
It is an object of the present invention to obviate or mitigate at least some of the above disadvantages.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a forward error correction system for reducing the transmission error in a data transmission. The system comprises an encoder for encoding input data, an interleaver for interleaving the encoded data to an output data stream and a first buffer operatively associated with the interleaver for storing the interleaved data. A transmitter is operatively associated with the first buffer for transmitting the interleaved data. A deinterleaver deinterleaves the transmitted interleaved data received from the transmitter and a second buffer operatively coupled with the deinterleaver stores the deinterleaved data. A decoder operatively coupled with the second buffer decodes the deinterleaved data. The deinterleaved data is decoded without intermediate storage.
In accordance with a further aspect of the present invention, there is provided a forward error correction encoder for receiving a plurality of different data streams and reducing the transmission error in a data transmission. The forward error correction encoder comprises a plurality of interleavers, each associated with respective ones of the data streams for interleaving data and a plurality of buffers associated with respective ones of the interleavers for storing the interleaved data. A plurality of deinterleavers is operatively associated with the buffers for providing deinterleaved data. An encoder encodes the deinterleaved data, and the encoded data is coupled with respective ones of the data streams. A transmitter is operatively associated with the buffers for transmitting the interleaved encoded data.
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Allen Kenneth R.
Catena Networks, Inc.
Townsend and Townsend / and Crew LLP
Tu Christine T.
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