System and method for forming stacked fin structure using...

Details System and method for forming stacked fin structure using... System and method for forming stacked fin structure using...

2005-05-17

2005-05-17

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S067000, C257S618000, C257S270000, C438S151000, C438S157000, C438S283000, C438S588000

Reexamination Certificate

active

06894337

ABSTRACT:
A method facilitates the formation of a stacked fin structure for a semiconductor device that includes a substrate. The method includes forming one or more oxide layers on the substrate and forming one or more amorphous silicon layers interspersed with the one or more oxide layers. The method further includes etching the one or more oxide layers and the one or more amorphous silicon layers to form a stacked fin structure and performing a metal-induced crystallization operation to convert the one or more amorphous silicon layers to one or more crystalline silicon layers.

REFERENCES:
patent: 6312979 (2001-11-01), Jang et al.
patent: 6762483 (2004-07-01), Krivokapic et al.
Digh Hisamoto et al., “FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFET: PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.

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