Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-07-29
2011-10-18
Choe, Yong (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S141000, C711S146000, C711SE12001, C711SE12017, C711SE12026
Reexamination Certificate
active
08041899
ABSTRACT:
A write back allocate system that includes: (i) a store request circuit; (ii) a processor, adapted to generate a store request that comprises an information unit and an information unit address; and (iii) a cache module, connected to the store request circuit and to a high level memory unit. A single cache module line includes multiple segments, each segment is adapted to store a single information unit. A content of a cache module line is retrieved from the high level memory unit by generating a fetch burst that includes multiple segment fetch operations. The store request circuit includes a snooper and a controller. The snooper detects a portion of an address of a cache segment of a cache line that is being fetched during a fetch burst. The controller is adapted to request from the cache module to receive the information unit before a completion of the fetch burst if the portion of the address of the cache segment matches a corresponding portion of the information unit address.
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PCT Application No. PCT/US2009/042021; Search Report and Written Opinion mailed Dec. 17, 2009.
Godin Kostantin
Landa Roman
Peled Itay
Tokar Yakov
Zamsky Ziv
Choe Yong
Freescale Semiconductor Inc.
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