System and method for fast interconnect delay estimation...

Details System and method for fast interconnect delay estimation... System and method for fast interconnect delay estimation...

2000-09-29

2003-07-29

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06601223

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a system and method of estimating time delay in integrated circuit design in general, and, in particular, to a system and method for estimating the interconnect delay in a Very Large System Integration (VLSI) circuit.
2. Description of the Related Art
VLSI circuits are commonplace in processor chips, whether for microprocessors, embedded devices, Digital Signal Processors (DSPs), etc. VLSI circuits are designed by groups of engineers who prepare detailed layout drawings, usually using Computer Aided Design (CAD) tools. These layouts macroscopically present the extremely complex pattern of active elements (such as transistors) and passive elements (such as interconnects) which, when photo-etched, doped, and deposited onto a silicon matrix, will collectively constitute the finished chip, which may include millions of microscopic parts, all interconnected according to a design.
The sequence of manufacturing steps required to produce such a VLSI chip in quantity is correspondingly complex. Thus, from initial design to setup of the manufacturing line, introduction of a new VLSI chip is an extremely expensive process, and not to be initiated lightly.
A major technical consideration underlying any new chip design is the maximum clock frequency at which the chip will operate in situ. If the frequency must, for the particular application, be greater that that at which a chip according to the particular design can operate, failure of the chip to function properly—or literal failure of the chip—can be the result.
It is important, therefore, in the process of designing a new chip or in implementing its manufacture, to determine, if possible, the maximum clock frequency at which the chip will operate. Obviously, if the maximum operating frequency can be determined at the analytical design point, before a significant investment in the manufacturing line has been made, a great deal of money can be saved by redesign, if the chip, when manufactured, will not operate properly at the frequency required. And even if, at a subsequent point in the process, the design must be altered—or even abandoned and replaced with an entirely new project—this might ultimately prove to be a prudent investment.
Additionally, although such cost savings can be easily appreciated in respect to a VLSI chip with millions of active components and interconnects, the potential savings which can thus be realized in the case of even a relatively simple Integrated Circuit (IC), incorporating only thousands of elements, can likewise be quite significant.
Therefore, there is a need to effectively determine, at a preliminary design phase, if possible, the extent to which a proposed chip—of whatever level of complexity—can be driven at or above the required clock frequency. This requires analysis of the time delay—from selected input to selected output points—of a signal input to the chip. In other words, it is necessary to determine the voltage response as a function of time.
One source of considerable transmission delay is the interconnects between active elements. Although it would be ideal if interconnects were loss-free—i.e., totally devoid of impedance—this is, unfortunately, not the case in the real world. Each interconnect does demonstrate a degree of resistance, capacitance, and, to a considerably lesser degree, inductance. While such impedance might be almost negligible in a single interconnect, even an extremely small value will have a significant effect on the maximum response speed of the circuit. Collectively, the delay caused by possibly millions of such interconnects will have a profound effect on reducing the maximum operating efficiency. In fact, interconnect delays represent an increasingly dominant portion of overall circuit delays in deep-submicron integrated circuit design.
In order to effectively predict the effect of interconnect delay, several methods have been employed by circuit designers. Because an exact solution of the time delays in interconnects requires the solution of a set of complex differential equations, circuit designers rely upon simplifications and modeling to come up with timing estimates. A commonly used model represents interconnects as resistors and capacitances in series and parallel. This model produces an RC (Resistance-Capacitance) tree, as shown in FIG.
1
.
An RC tree, or any net topology tree, is generated from a design model, a directed graph representing the “netlist” of the logic design. Each pin in an IC is associated with a “cell”. Each cell has an associated location, the x,y coordinates of the cell in the IC. Also associated with each cell is physical information which provides the cell dimensions and the pin offsets relative to the cell origin. The cell location and pin offsets may be combined to determine the locations of each source and sink pin on a net. A net topology tree may then be generated from this data. The tree may be estimated using, for example, a minimum Steiner tree. Or, an actual or preferred wire route produced by a routing tool may be used. Once a tree has been generated, an interconnect delay estimator may use that tree to perform its calculations. C and R for each segment of the tree are computed using a set of technology constants specifying the capacitance and resistance per unit length. There may be only a single set of constants for all wires in any direction, or there may be different sets of constants for horizontal and vertical wires or for wires on different wiring planes.
Once an RC tree representation has been made, circuit designers use a simplified estimation metric to calculate the time delay. Among these simplified estimation metrics, the lumped RC delay and Elmore delay metrics are some of the most widely used techniques. These techniques will be described below.
Lumped RC Delay Model
The lumped RC delay model is a highly simplified estimation metric of the interconnect delay. It is well known that the response of a simple RC circuit to a step function is given as V(t)=V
0
(1−e
−t/RC
). This implies that the step input delay through the 50% point (V
0
/2 ) of the output waveform for a simple RC circuit is given as 0.7*RC. This delay metric represents the time constant (0.7) obtained by multiplying the total wire resistance from source to sink with the total net capacitance (RC).
For example, for the RC tree shown in
FIG. 1
, total resistance from source S to node
7
is R
1
+R
2
+R
4
+R
7
and the total lumped net capacitance is C
total
=(C
S
+C
1
+C
2
+C
3
+C
4
+C
5
+C
6
+C
7
). Thus, the interconnect delay from source S to node
7
according to lumped RC delay metric is given as 0.7*(R
1
+R
2
+R
4
+R
7
)*C
total
. Similarly, the lumped RC delay from source to various nodes is given as follows (where T
S−1
is the delay time from source S to node 1):
T
S−1
=0.7*(
R
1
)*(
C
total
)
T
S−2
=0.7*(
R
1
+R
2
)*(
C
total
)
T
S−3
=0.7*(
R
1
+R
3
)*(
C
total
)
T
S−4
=0.7*(
R
1
+R
2
+R
4
)*(
C
total
)
T
S−5
=0.7*(
R
1
+R
3
+R
5
)*(
C
total
)
T
S−6
=0.7*(
R
1
+R
3
+R
6
)*(
C
total
)
T
S−7
=0.7*(
R
1
+R
2
+R
4
+R
7
)*(
C
total
)
Although the lumped RC delay model is computationally very efficient, it is highly inaccurate as compared to real interconnect delays.
Elmore Delay Model
One of the most popular delay metrics for RC trees has been the Elmore delay model because of its simplicity and high degree of correlation to real delays. Elmore originally estimated the 50% delay of a monotonic step response by the mean of the impulse response. W. C. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wide-band Amplifiers”,
Journal of Applied Physics,
Vol.19, pp. 55-63, January 1948. Penfield and Rubenstein proved that the response of a general RC tree to a step input is monotonic. J. Rubinstein, P

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