Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-03-28
2004-08-24
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S013000, C714S741000
Reexamination Certificate
active
06782518
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is related to co-pending applications entitled “System and Method for Verifying Superscalar Computer Architectures”, Ser. No. 10/113,756, and “System and Method for Facilitating Programmable Coverage Domains for a Testcase Generator”, Ser. No. 10/113,319 which were both filed on Mar. 28, 2002 and are incorporated herein by reference in their entireties.
FIELD OF THE INVENTION
This invention relates to integrated circuit testing and, more particularly, the invention relates to a method and system for facilitating coverage feedback testcase generation reproducibility.
BACKGROUND OF THE INVENTION
The proliferation of modern electronics into our everyday lives is due in large part to the existence, functionality and relatively low cost of advanced integrated circuits. As technology moves ahead, the sophistication of integrated circuits increases. An important aspect of designing an advanced integrated circuit is the ability to thoroughly test the design of the integrated circuit to assure the design complies with desired architectural, performance, and design parameters. Testing a complex integrated circuit such as a superscalar microprocessor requires the generation of a large number of instruction sequences to assure that the microprocessor behaves properly under a wide variety of circumstances.
Verification techniques generally require automated testing systems that can turn out high volume testcases in an effort to sufficiently cover the realm of possible behaviors of the integrated circuit being tested. Testcases may be generated by a testcase generator in accordance with parameters specified in a file that are provided by a software design specialist or engineer, otherwise the generator generates random testcases.
Verification of microprocessors usually entails the definition of coverage domain(s) for use in measuring the effectiveness of various testcases and testcase generators. These domains are typically static once they are created and are persistent across the entire duration of the verification phase of a development cycle. The resulting coverage information from the testcase is collected and recorded for each entry in these domains and typically kept in a large central database as a cumulative history. These domains are typically a cross-product of various components of the machine state, instructions, and instruction results. For example, where an instruction=“w”, addressing mode(s)=“x”, translation mode(s)=“y”, and resulting condition codes=“z”, the corresponding state space would equal w*x*y*z. As one might suspect, this state space can grow quite large and maintaining records for each state can be memory/compute intensive. Further, adding sequences of events to the coverage domain would expand this state space exponentially.
When using this coverage domain information in a testcase generator employing an internal coverage feedback system for generating “interesting” (e.g., unusual, rare) testcases, maintaining the smallest domain is optimal. It would also be beneficial to generate testcases based only on what has transpired in the current generation session, in addition to referencing the total cumulative coverage history. Other desirable functions include generating a comprehensive test suite, allowing user control over coverage policies, profiling initialization settings, and profiling generation tools.
There may be times when it is desirable to reproduce a testcase that was generated with coverage feedback. One known method of reproducing a testcase is to regenerate all prior testcases 1, 2, . . . , n−1. This is slow and inefficient. When coverage feedback mechanisms are employed in testcase generation, the pseudo-random seed is not the only factor influencing decisions, but can also include the current state of the defined coverage domain element(s). Thus, the coverage state at the time of generating testcase ‘n’ must be reproduced.
SUMMARY OF THE INVENTION
An exemplary embodiment of the invention relates to a system and method for facilitating coverage feedback testcase generation reproducibility. The system comprises a testcase generator comprising an instruction generator and an instruction simulator; an internal coverage domain accessible to the testcase generator, a regeneration file storing updated testcase data; and a temporary holding structure. The internal coverage domain comprises: coverage domain elements; a session component; and a prior cumulative history component. Upon generating a testcase by the testcase generator, a regeneration file is constructed utilizing testcase data updates acquired during execution of the testcase. The updates are provided by the temporary holding structure. The invention also comprises a method and storage medium.
The above-described and other features and advantages of the present invention will be appreciated and understood by those skilled in the art from the following detailed description, drawings, and appended claims.
REFERENCES:
patent: 3764995 (1973-10-01), Helf et al.
patent: 4513418 (1985-04-01), Bardell, Jr. et al.
patent: 4519078 (1985-05-01), Komonytsky
patent: 5202889 (1993-04-01), Aharon et al.
patent: 5475608 (1995-12-01), Masuoka
patent: 6041419 (2000-03-01), Huang et al.
patent: 6041429 (2000-03-01), Koenemann
patent: 6125359 (2000-09-01), Lautzenheiser et al.
patent: 6212667 (2001-04-01), Geer et al.
patent: 6397169 (2002-05-01), Shenoy et al.
patent: 6584598 (2003-06-01), Rao et al.
patent: 6634017 (2003-10-01), Matsui et al.
patent: 0549949 (1993-07-01), None
A.K. Chandra, V.S. Iyengar, R.V. Jawalekar, M.P. Mullen, I.Nair, and B.K. Rosen, “Architectural Verification of Processors Using Symbolic Instruction Graphs,” 1994, pp. 454-459.
A. Chandra, V. Iyengar, D. Jameson, R. Jawalekar, I. Nair, B. Rosen, M. Mullen, J. Yoon, R. Armoni, D. Geist and Y. Wolfsthal AVPGEN—A Test Generator for Architecture Verification, IEEE Transactions on Very Large Scale Integration Systems, vol. 3, No. 2, Jun. 1995 pp. 188-200.
Cantor & Colburn LLP
Garbowski Leigh M.
Luu Chuong Anh
Wojnicki, Jr. Andrew
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