Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-10-31
2004-04-06
Auve, Glenn A (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C370S392000, C370S475000
Reexamination Certificate
active
06718419
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to high-speed data communications. More specifically, the invention relates to a system and method for extending the number of addresses on a data bus without increasing the number of address control bits used to identify a particular addressable device on the data bus.
BACKGROUND OF THE INVENTION
The present communications infrastructure supporting voice, video, and data networks is founded on technology that is over 30 years old. In spite of their age, these networks have served the telecommunications industry well, even in recent times, for they provide a cohesive foundation on which to build the modern telecommunications infrastructure. In the early 1970s, packet switching technology was introduced to support emerging data networks. At about the same time packet switching networks were being deployed, the International Telecommunications Union-Telecommunications Standard Sector (ITU-T, formerly the CCITT) published the X.25 specification. X.25 defines the procedures for computers to communicate with network machines (packet switches) and to transport data to other computers. X.25 has become a widely used industry standard. X.25 was designed for the data systems that operate at only a few bits per second or a few hundred bits per second. Although X.25 can be placed on very-high speed media and can operate quite efficiently at these relatively high speeds, a substantial amount of subscriber equipment and software has been designed for modest data transfer rates. With ever increasing processing speed of today's personal computers and other data transfer devices, greater transfer rates are in demand.
This demand for increased transfer rates in data communications networks, the advent of relatively error-free high-capacity networks, and the implementation of very powerful end-user workstations has led to a criticism of the overhead and redundancy built into the X.25 protocol. For example, sequencing and flow control, as well as, positive acknowledgements and negative acknowledgements are performed at least twice in accomplishing data transfers with X.25.
In response, most of today's emerging technology is based on the idea of relaying data traffic as quickly as possible. This concept is often called fast packet relay or fast packet switching. Currently, both frame relay and cell relay are popular forms for transporting data traffic. In contrast to frame relay, cell relay uses a fixed length protocol data unit (PDU) called a cell. Cell relay presents an integrated solution to networking in that it supports the transmission and reception of voice, video, data, and other applications. This capability is of particular interest to large companies that may have developed multiple networks to handle different data transmission schemes.
Asynchronous transfer mode (ATM) is a popular cell relay protocol designed to provide a high speed, low-delay multiplexing and switching network protocol to support any type of user traffic. ATM segments and multiplexes user traffic into small, fixed length cells comprising a header and a user payload. ATM provides no error detection on the contents of the user payload. In addition, ATM provides no retransmission services and very few operations are performed on the header. The intention of this approach—small cells with minimal services—is to implement a network fast enough to support multi-megabit transfer rates.
Multiple protocols are required to support full ATM operations. The number of protocols required depends upon where the user traffic is being transported. For example, data traffic may traverse user network interfaces (UNIs), network node interfaces (NNIs), data exchange interfaces (DXIs), and frame user network interfaces (FUNIs). The UNI is the most visible protocol, because it defines the procedures for the internetworking between the user equipment and an ATM node. Two forms of UNIs are supported, a private UNI and a public UNI. The major difference between the private and the public UNI pertains to the physical communications links between the machines. A twisted-pair or a private fiber will typically support a private link, whereas, a public UNI will typically consist of a DS3, or a synchronous digital hierarchy/synchronous optical network (SDH/SONET) communications link.
The ATM Forum is a standards body charged with promulgating operational standards, which support all the various data transfers (protocols) in an ATM based data network. The Universal Test & Operations Physical Interface for ATM (UTOPIA) represents just one of many operational standards that support ATM data transfers in ATM networks. The ATM Forum has approved four versions of the UTOPIA standard. They are commonly known as UTOPIA-Levels 1 through 4. Hardware devices compliant with the UTOPIA-Level 3 standard are just becoming commercially available. UTOPIA-Level 4 devices are still under development.
The UTOPIA-Level 2 standard introduced at least two important changes to the original UTOPIA-Level 1 standard. First, Level 2 increased the bandwidth to support at least 622.08 Mbps, the bandwidth of STS12/STM4 in the SDH/SONET hierarchy. This change was implemented by increasing the width of the data path to 16 bits and the operating frequency to support timing specifications of 25, 33, and 50 MHz. Second, Level 2 introduced addressing capabilities to support the interaction of multiple physical layer devices to the same ATM layer device. This modification is especially important for “last mile” links to end-user devices where multiple digital subscriber line (xDSL) communication systems (each with a relatively low bandwidth per physical device) are used to traverse the gap between the ATM layer device and the end-user device(s). The standard version of the UTOPIA Level 2 addressing scheme suffers from at least two shortcomings: the address scheme supports only thirty-two addresses and one of the addresses is reserved for a “dummy” device to avoid bus contention.
In light of the expected implementation and operational cost erosion for all data interface technologies, it is highly desirable to identify and implement communication links that exhibit increased performance with minimal added cost and complexity. With this goal in mind, there is a need for an improved system and method that can increase the bandwidth of a communication link between two computing devices at the interface between an ATM layer device and various available physical layer transport links while minimizing installation and operational complexity, space requirements, and cost.
SUMMARY OF THE INVENTION
In light of the foregoing, the invention is a system and a method for extending the number of addresses on a data bus without modifying the number of address bits (address lines) used to identify the various devices on the data bus. An improved ATM network node configured with a data bus extender in accordance with the present invention may achieve an overall higher level of data transfer efficiency by increasing the number of addressable physical layer transport devices that may communicate with an ATM layer device. The ATM network node of the present invention achieves increased performance with a minimal hardware investment at the source or ATM layer device. A data bus extender in accordance with the present invention may comprise an address stripper and a range select decoder wherein at least one of the address bits at the slave or physical layer device side is enabled by the range select decoder.
The present invention can also be viewed as providing a method for extending the number of addressable communication devices on a data bus. In its broadest terms, the method can be described by the following steps: receiving an address at a master device; subdividing the addressable slave devices into a plurality of ranges; identifying an appropriate range in response to a first portion of the address; identifying a particular device within the identified range responsive to a second portion of the address; selecting an uniquely ide
Auve Glenn A
Globespanvirata, Inc.
Thomas Kayden Horstemeyer & Risley
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