System and method for examining high-frequency clock-masking...

Details System and method for examining high-frequency clock-masking... System and method for examining high-frequency clock-masking...

2007-10-30

2007-10-30

Nghiem, Michael P. (Department: 2863)

Data processing: measuring, calibrating, or testing

Testing system

Signal generation or waveform shaping

Reexamination Certificate

active

11168722

ABSTRACT:
The present invention provides for a method for examining high-frequency clock-masking signal patterns at a reduced frequency. A first mode of a first shift register is selected. A plurality of bits is loaded on the first shift register at a first frequency. A second mode of the first shift register is selected. A first mode of a second shift register is selected. The plurality of bits is loaded on the second shift register. A second mode of the second shift register is selected. A first mode of a third shift register is selected. The plurality of bits is loaded on the third shift register. A second mode of the third shift register is selected and the plurality of bits is loaded from the third shift register at a second frequency, where the second frequency is lower than the first frequency, thereby providing for examining high-frequency clock-masking signal patterns at a reduced frequency.

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“Circuit to Reduce Transient Current Swings During Mode Transistions of High Frequency/High Power Chips” U.S. Appl. No. 10/981,154, filed Nov. 4, 2004.

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