System and method for evaluating vias per pad in a package...

Details System and method for evaluating vias per pad in a package... System and method for evaluating vias per pad in a package...

2005-06-14

2005-06-14

Whitmore, Stacy A. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06907589

ABSTRACT:
A method and software product evaluate vias, per pad, in an electronic design. One or more via per pad rules are formulated, and then the electronic design is processed to determine whether the vias of the electronic design violate the via per pad rules. In the event of a violation, one or more indicators are generated to identify vias that violate the via per pad rules. The indicators are visual indicators (e.g., via per pad DRCs) on a graphical user interface, and/or a textual report summarizing violations.

REFERENCES:
patent: 5963729 (1999-10-01), Aji et al.
patent: 6072945 (2000-06-01), Aji et al.
patent: 6086627 (2000-07-01), Bass et al.
patent: 6417463 (2002-07-01), Cornelius et al.
patent: 6829754 (2004-12-01), Yu et al.

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