System and method for evaluating signal trace...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

06938230

ABSTRACT:
A method evaluates signal trace discontinuities in an electronic design of the type having one or more traces. The method includes the steps of formulating one or more trace discontinuity rules, processing the electronic design to determine whether the traces violate the trace discontinuity rules, and generating an indicator (e.g., a DRC) associated with the electronic design to identify violated trace discontinuity rules. Each level, each signal net, or a group of signal nets may be evaluated, for example, to ensure compliance with the trace discontinuity rules.

REFERENCES:
patent: 5610833 (1997-03-01), Chang et al.
patent: 5808529 (1998-09-01), Hamre
Wing,“On VLSI Interconnects”,Jun. 1991, IEEE Conference Proceedings, International Conference on Circuits and System, vol. 2, pp. 991-996.
Venkataraman et al.,“Effects of Discontinuities (Vias) on High Speed Interconnects”, Nov. 1994, IEEE 3rdTopical Meeting on Electrical Performance of Electronic Packaging, pp. 79-82.
Boussetta et al., “Modeling of Multiconductor Microstrip Bend Discontinuities” Nov. 1994, IEEE 3rd Topical Meeting on Electrica Performance of Electronic Packaging, pp. 148-150.
Kergonou et al.,“Frequency Dependence in High Speed Interconnections”, Aug. 2001, IEEE International Symposium on Electromagnetic Compatibility, vol. 1, pp. 632-634.

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