Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-09-18
2007-09-18
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10368789
ABSTRACT:
A method and software product evaluate vias in an electronic design. One or more via sufficiency rules are formulated, and then the electronic design is processed to determine whether the vias of the electronic design violate the via sufficiency rules. In the event of a violation, one or more indicators are generated to identify vias that violate the via sufficiency rules. The indicators are visual indicators (e.g., via insufficiency DRCs) on a graphical user interface, and/or a textual report summarizing violations.
REFERENCES:
patent: 6026224 (2000-02-01), Darden et al.
patent: 6417463 (2002-07-01), Cornelius et al.
patent: 6613592 (2003-09-01), Chen et al.
patent: 6615400 (2003-09-01), Lukanc
patent: 6727169 (2004-04-01), Raaijmakers et al.
patent: 6829754 (2004-12-01), Yu et al.
patent: 2003/0051218 (2003-03-01), Kumagai
patent: 2004/0063228 (2004-04-01), Li et al.
Bertrand Nathan
Frank Mark D.
Nelson Jerimy
LandOfFree
System and method for evaluating power and ground vias in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for evaluating power and ground vias in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for evaluating power and ground vias in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3778637